Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 2 of 3

September 2014

452

Order Number: 330061-002US

The possible causes of wake events (and their restrictions) are shown in 

.

1. Reset Type 5 is when the state goes straight to S5 and the host stays there. See the description in 

RTC Alarm

RTC

Internal Set the RTC_EN bit in the PM1_STS_EN register.

Y

PMU_PWRBTN_B 

(Power Button)

SUS

Pin

Always enabled as a wake event

Y

Y

GPIO_SUS0..3

SUS

Pin

GPE0_EN register (after having gone to S5 via SLP_EN 

but not after a power failure)

GPIOs that are in the core well are not capable 

of waking the system from sleep states where 

the core well is not powered. 

Y

PMU_WAKE_B 

(PCI Express* 

WAKE#)

SUS

Pin

PCIEXP_WAKE_DIS bit

When the WAKE# pin is active and the 

PCIEXP_WAKE_DIS bit is clear, the SoC wakes 

the platform.

Y

PMU_WAKE_LAN_B 

(GbE Wake#)

SUS

Internal Internal signal from GbE to the PMC

Y

Classic USB

SUS

Internal Set the USBn_EN bit(s) in the GPE0_EN register.

Y

Power Management 

Events

SUS

Internal

PME_B0_EN bit in the GPE0_EN register. This wake 

status bit includes multiple internal agents:

• Integrated  LAN
• EHCI (USB)
• SATA

SATA can only trigger a wake event in S1 (not 

supported by the SoC), but if it had asserted 

its PME prior to the S5 entry and the software 

does not clear PME_B0_STS, a wake event 

would still result.

Y

PCI_EXP PME 

Messages

N/A

N/A

Since the SoC does not support the S1 sleep state, the 

platform design must use the PCI Express WAKE# pin 

rather than the messages for wake from S5. 

PMC Initiated

SUS

Internal

No enable bits. The PMC firmware can wake the host 

independent of the other wake events listed, if desired. 

A bit is provided in PRSTS for reporting this wake event 

to the BIOS. 

This wake event may be used as a wake 

trigger on behalf of some other wake source.

Y

Y

Integrated WOL 

Enable Override

SUS

Internal WOL Enable Override Bit (in the configuration space)

Y

Y