Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

481

A variety of Serial Flash devices exist in the market. For a Serial Flash device to be 

compatible with the SPI bus, it must meet the minimum requirements detailed in the 

following sections of this document.

The SPI Flash device must meet the following minimum requirements when used 

explicitly for the system BIOS storage:

• The erase size has at least one of the following: 64 Kbytes, 8 Kbytes, 4 Kbytes, or 

256 bytes.

• The device must support multiple writes to a page without requiring a preceding 

erase cycle (refer to 

).

• The Serial Flash device must ignore the upper address bits such that an address of 

FF_FFFFh aliases to the top of the Flash memory.

• SPI Compatible Mode 0 support (the clock phase is 0 and data is latched on the 

rising edge of the clock).

• If the device receives a command that is not supported or incomplete (less than 8 

bits), the device must complete the cycle gracefully without any impact on the 

Flash content.

• An Erase command (page, sector, block, chip, etc.) must set all bits inside the 

designated area (page, sector, block, chip, etc.) to 1 (Fh).

• Status register bit 0 must be set to 1 when a write, erase, or write to a status 

register is in progress and cleared to 0 when a write or erase is NOT in progress.

• Devices requiring the Write Enable command must automatically clear the write 

enable latch at the end of data program instructions.

• Byte write must be supported. The flexibility to perform a write between 1 byte to 

64 bytes is recommended.

• Hardware sequencing requirements are optional in the BIOS-only platforms.
• SPI Flash devices that do not meet the hardware sequencing command set 

requirements may work in the BIOS-only platforms using software sequencing.