Intel C2518 FH8065501516710 Data Sheet
Product codes
FH8065501516710
Volume 2—Serial Interrupt Controller—C2000 Product Family
Architectural Overview
Intel
®
Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 2 of 3
September 2014
496
Order Number: 330061-002US
23.2.6
Data Frame Format and Issues
shows the format of the data frames. The decoded serial INT[A:D]# values
are internally ANDed in the SoC with the corresponding PCI Express* input signals
(PIRQ[A:D]#). Therefore, these four interrupts are shared.
The other interrupts decoded via SERIRQ are also ANDed with the corresponding
internal interrupts. For example, if the interrupt vector for IRQ10 is set to be used as
the System Control Interrupt (SCI) vector, then it is ANDed with the decoded value for
IRQ10 from the SERIRQ stream.
Table 23-4. SERIRQ Interrupt Decoding and Mapping
Data
Frame #
Interrupt
Clocks Past
Start Frame
Comment
1
IRQ0
2
Ignored. This is only generated via the internal 8524 PIT.
2
IRQ1
5
3
SMI#
8
4
IRQ3
11
5
IRQ4
14
6
IRQ5
17
7
IRQ6
20
8
IRQ7
23
9
IRQ8
26
Ignored. IRQ8# is only generated internally by the SoC.
10
IRQ9
29
11
IRQ10
32
12
IRQ11
35
13
IRQ12
38
14
IRQ13
41
Ignored
15
IRQ14
44
Ignored
16
IRQ15
47
17
IOCHCK#
50
Same as ISA IOCHCK# going active
18
PCI INTA#
53
19
PCI INTB#
56
20
PCI INTC#
59
21
PCI INTD#
62