Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

507

The LPC Firmware Memory Read and Write cycles are intended for the system-boot 

firmware, although they can be used for any LPC memory cycle. The Sync time 

depends on the speed of the device. For more information about the Firmware Memory 

Read and Write cycles, see the “Firmware Memory Cycles” section of the Intel

Count (LPC) Interface Specification, Revision 1.1. Configuring the SoC to use the LPC 

for system boot instead of the SPI interface is outlined in 

For LPC memory cycles below 16M (100_0000h), the SoC LPC Controller performs 

standard LPC memory cycles. For cycles targeting firmware (BIOS boot code located at 

or above 16M), Firmware Memory cycles are used. Only 8-bit transfers are performed. 

When a larger transfer appears, the LPC controller breaks it into multiple 8-bit transfers 

until the request is satisfied. If the cycle is not claimed by any peripheral, and 

subsequently aborted, the LPC controller returns a value of all 1’s to the CPU.