Intel C2518 FH8065501516710 Data Sheet
Product codes
FH8065501516710
Volume 2—Low Pin Count (LPC) Controller—C2000 Product Family
Power Management
Intel
®
Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 2 of 3
September 2014
506
Order Number: 330061-002US
24.2.5
Port 80 POST Code Register Redirection
The iLB has 16, 1-byte registers accessible in the I/O space at 80h - 8Fh. They are
written and read by the software. I/O writes to these locations also pass the write data
to the LPC bus for attached POST code displays or indicators typically used for debug
purposes. I/O reads by the software to these locations only read the iLB registers and
do not result in any LPC transactions.
24.2.6
System Error (SERR)
When an error code (1010) is received on the sync cycle, the LPC controller signals a
System Error (SERR) to the core. This occurs only if the SERR reporting is enabled for
the LPC.
24.3
Power Management
24.3.1
LPCPD# Protocol
Note:
24.3.2
Clock Run (CLKRUN)
24.3.3
LPC Clock Enabling