Intel C2518 FH8065501516710 Data Sheet

Product codes
FH8065501516710
Page of 746
Intel
®
 Atom™ Processor C2000 Product Family for Microserver
September 2014
Datasheet, Vol. 2 of 3
Order Number: 330061-002US
523
Volume 2—Real Time Clock (RTC)—C2000 Product Family
Architectural Overview
26.3
Architectural Overview
The RTC module provides a battery backed-up date and time keeping device. Three 
interrupt features available are time of day alarm with once-a-second to once-a-month 
range, periodic rates of 122 ms to 500 ms, and end-of-update cycle notification. 
Seconds, minutes, hours, days, day of week, month, and year are counted. The hour is 
represented in a twelve or twenty-four hour format, and data are represented in BCD 
or binary format. The design is meant to be functionally compatible with the Motorola* 
MS146818B. The time keeping comes from a 32.768-kHz oscillating source, which is 
divided to achieve an update every second. The lower 14 bytes on the lower RAM block 
have specific functions. The first ten are for time and date information. The next four 
(0Ah to 0Dh) are registers, which configure and report RTC functions. A host-initiated 
write takes precedence over a hardware update if a collision.
26.3.1
Update Cycles
An update cycle occurs once a second, if the B.SET bit is not asserted and the divide 
chain is properly configured. During this procedure, the stored time and date are 
incremented, overflow checked, a matching alarm condition is checked, and the time 
and date are rewritten to the RAM locations. The update cycle starts at least 488 ms 
after A.UIP is asserted, and the entire cycle does not take more than 1984 ms to 
complete. The time and date RAM locations (00h to 09h) are disconnected from the 
external bus during this time.
26.3.2
Interrupts
The real-time clock interrupt is internally routed within the SoC both to the I/O APIC 
and the 8259. It is mapped to interrupt vector 8. This interrupt does not leave the SoC, 
nor is it shared with any other interrupt. IRQ8# from the Serial IRQ (SERIRQ) stream is 
ignored. However, the High Performance Event Timers (HPET) are also mapped to 
IRQ8#; in this case, the RTC interrupt is blocked.
26.3.3
Lockable RAM Ranges
Once a range is locked, the range is unlocked only by a hard reset, which invokes the 
BIOS and allow it to re-lock the RAM range.