Intel C2518 FH8065501516710 Data Sheet

Product codes

FH8065501516710

Volume 2—Real Time Clock (RTC)—C2000 Product Family

RTC During Power-Up

Intel

Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 2 of 3

September 2014

524

Order Number: 330061-002US

26.4

RTC During Power-Up

The RTC circuitry is always powered-on to update the real time clock. It receives its

supply voltage from the connected coin cell. When the power-up sequence begins and

the other platform-board power supplies are available, the RTC unit moves to an

alternative power supply.

26.5

Clearing the Battery-Backed RTC RAM

Clearing the CMOS RAM in an SoC-based platform is done by using a jumper on

SRTCRST_B or through a jumper tied to a dedicated general-purpose I/O port. Do not

attempt to clear CMOS by using a jumper to tie Vss to the RTC 3.3V power pin

(VCCRTC_3P3).

26.5.1

Using SRTCRST_B to Clear CMOS Registers

A jumper on SRTCRST_B clears the CMOS values as well as resets to default, the state

of those configuration bits that reside in the RTC power well. When the SRTCRST_B is

strapped to ground, the bit of the RTC_PWR_STS (RPS) bit of the General PM

Configuration 1 (GEN_PMCON1 ) register is set and those configuration bits in the RTC

power well are set to their default state. The BIOS monitors the state of this bit and

manually clears the RTC CMOS array once the system is booted. The normal position

causes SRTCRST_B to be pulled up through a weak pull-up resistor.

Ta ble 26-3

shows

which bits are set to their default state when SRTCRST_B is asserted.

This SRTCRST_B jumper technique allows the jumper to be moved and then replaced

while the system is powered-off. Then, once booted, the G EN_PMCON1.RPS bit is

detected in the set state.

Table 26-3. Register Bits Reset by Asserting SRTCRST_B

Register Bit

Bit(s)

Default State

RCRB_GENERAL_CONTROL.TS

GEN_PMCON1.PME_B0_S5_DIS

GEN_PMCON1.WOL_EN_OVRD

GEN_PMCON1.DIS_SLP_X_STRCH_SUS_UP

GEN_PMCON1.RTC Reserved

GEN_PMCON1.SWSMI_RATESEL

7:6

00b

GEN_PMCON1.S4MAW

5:4

00b

GEN_PMCON1.S4ASE

GEN_PMCON1.AG3E

PM1_STS_EN.RTC_EN

PM1_STS_EN.PWRBTNOR_STS

PM1_CNT.SLP_TYP

12:10

GPE0a_EN.PME_B0_EN

GPE0a_EN.BATLOW_EN