Intel C2518 FH8065501516710 Data Sheet
Product codes
FH8065501516710
Volume 2—8254 Programmable Interval Timer (PIT)—C2000 Product Family
Architectural Overview
Intel
®
Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 2 of 3
September 2014
532
Order Number: 330061-002US
27.3.2
Counter 0, System Timer
I/O address 0x40h: Counter 0
This counter functions as the system timer by controlling the state of IRQ0 and is
programmed for mode 3 operation.
The counter produces a square wave with a period equal to the product of the counter
period (838 ns) and the initial count value. The counter loads the initial count value one
counter period after the software writes the count value to the counter I/O address.
The counter initially asserts IRQ0 and decrements the count value by two each counter
period. The counter negates IRQ0 when the count value reaches 0. It then reloads the
initial count value and again decrements the initial count value by two each counter
period. The counter then asserts IRQ0 when the count value reaches 0, reloads the
initial count value, and repeats the cycle, alternately asserting and negating IRQ0.
27.3.3
Counter 1, Refresh Request Signal
I/O address 0x41h: Counter 1
27.3.4
Counter 2, Speaker Tone
I/O address 0x42h: Counter 2
Table 27-2. NSC Register Bits Used by the 8254 PIT
Name
Long Name
Description
5
T2S
Timer Counter 2 Status
Reflects the current state of the 8254 Counter 2 outputs.
4
RTS
Refresh Cycle Toggle Status
Reflects the current state of 8254 Counter 1.
1
SDE
Speaker Data Enable
0
TC2E
Timer Counter 2 Enable
When cleared, Counter 2 counting is disabled. When set,
counting is enabled.