Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

555

The poll mode conserves space in the interrupt vector table. Multiple interrupts that are 

serviced by one interrupt service routine do not need separate vectors if the service 

routine uses the Poll command. The poll mode is also used to expand the number of 

interrupts. The polling interrupt service routine calls the appropriate service routine 

instead of providing the interrupt vectors in the vector table. In this mode, the INTR 

output is not used and the microprocessor internal interrupt enable flip-flop is reset, 

disabling its interrupt input. Service to the devices is achieved by the software using a 

Poll command.

The Poll command is issued by setting OCW3.PMC. The PIC treats its next I/O read as 

an interrupt acknowledge, sets the appropriate ISR bit if there is a request, and reads 

the priority level. Interrupts are frozen from the OCW3 write to the I/O read. The byte 

returned during the I/O read contains a 1 in bit 7 if there is an interrupt and the binary 

code of the highest priority level in bits [2:0].

If the ELCR bit is 0, an interrupt request is recognized by a low-to-high transition on the 

corresponding IRQ input. The IRQ input remains high without generating another 

interrupt. If the ELCR bit is 1, an interrupt request is recognized by a high level on the 

corresponding IRQ input, and an edge detection is not needed. The interrupt request 

must be removed before the EOI command is issued to prevent a second interrupt from 

occurring.

In both the edge- and level-triggered modes, the IRQ inputs must remain active until 

after the falling edge of the first internal INTA#. If the IRQ input goes inactive before 

this time, a default IRQ7 vector is returned.

An EOI occurs in one of two fashions: by a command word write issued to the PIC 

before returning from a service routine

, 

the EOI command; or automatically when the 

ICW4.AEOI bit is set to 1.