Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

557

Each interrupt request is masked individually by the Interrupt Mask Register (IMR). 

This register is programmed through OCW1. Each bit in the IMR masks one interrupt 

channel. Masking IRQ2 on the master controller masks all requests for service from the 

slave controller.

Some applications may require an interrupt service routine to dynamically alter the 

system priority structure during its execution under software control. For example, the 

routine may wish to inhibit lower priority requests for a portion of its execution but 

enable some of them for another portion.

The special mask mode enables all interrupts not masked by a bit set in the Mask 

Register. Normally, when an interrupt service routine acknowledges an interrupt 

without issuing an EOI to clear the ISR bit, the interrupt controller inhibits all lower 

priority requests. In the special mask mode, any interrupts are selectively enabled by 

loading the mask register with the appropriate pattern.

The special mask mode is set by OCW3.ESMM=1b and OCW3.SMM=1b, and cleared 

where OCW3.ESMM=1b and OCW3.SMM=0b.