Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 2 of 3

September 2014

58

Order Number: 330061-002US

The DDR3 memory controller contains two independent DDR3 memory controllers. 

Each memory channel supports either one or two DIMMs, where each DIMM is either 

single- or dual-rank. The supported DRAM chip data width is x8. The SoC does not 

support x16 devices.

When only one of the two memory channels is used in a platform board design, 

Channel 0 must be used. In all designs, Channel 0 must be populated by DRAM 

devices.

Within each memory channel DIMMs are populated in slot order; slot 0 is populated 

first and slot 1 last.

If a DIMM has two ranks, the ranks must be symmetrical (same chip width, same chip 

density, and same total memory size per rank).

If both memory channels of the memory controller are used, then both channels must 

be populated identically (same width, same density, same rank, and same total 

memory size per rank).

Minimum memory capacity:

• All products = 2 GB (one memory controller, 1 rank, 8 banks, 2-Gbit-density 

components)

Maximum memory capacity:

• C2750 and C2550 products = 64 GB (two memory controllers, 2 ranks each, 8 

banks per rank, 8-Gbit-density components)

• C2730 and C2530 products = 32 GB (two memory controllers, 2 ranks each, 8 

banks per rank, 4-Gbit-density components)

• C2350 product = 16 GB (one memory controller, 2 ranks, 8 banks per rank, 4-Gbit-

density components)

The SoC memory controller supports the following features:

• DDR3 (1.5V) and DDR3L (1.35V)
• ECC enabled DIMMs and SODIMMs
• Non-ECC UDIMMs
• 1600 or 1333 MT/s depending on SKU
• UDIMM, SODIMM, VLP DIMM, and memory (solder) down are supported
• Device width support for only x8 devices
• Device density: 2, 4, or 8 Gb
• Number of ranks per channel: 1, 2, or 4
• DDR3 data scrambling to improve signal integrity (configurable)