Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 3 of 3

September 2014

580

Order Number: 330061-002US

DDR3_1_DQSB[7:0]

I/O

DDR

8

VDDR

DDR3 Data Strobes: During 

writes, driven by CDV offset 

so as to be centered in the 

data phase. During reads, 

driven by memory devices 

edge-aligned with data. The 

following list matches the data 

strobe with the data bytes: 

(DQS_7: DQ[63:56] …. 

DQS_0: DQ[7:0]). The data 

strobes may be used in single-

ended mode or paired with 

optional complementary 

signals DQS_B to provide 

differential-pair signaling to 

the system during both reads 

and writes. A control bit at 

EMR(1)[A10] enables or 

disables all complementary 

data strobe signals.

DDR3_1_DQSBECC[0]

I/O

DDR

1

VDDR

DDR3 ECC Strobe: 

Differential-pair output with 

read-data ECC, differential-

pair input with write-data 

ECC. Edge-aligned with read-

data ECC, centered in write-

data ECC.

DDR3_1_CK[3:0]

O

DDR

4

VDDR

DDR3 Differential Clock: All 

address and control input 

signals are sampled on the 

crossing of the positive edge 

of CK and negative edge of 

CKB. Output (read) data is 

referenced to the crossings of 

CK and CKB (both directions 

of crossing). 

DDR3_1_CKB[3:0]

O

DDR

4

VDDR

DDR3 Differential Clock: All 

address and control input 

signals are sampled on the 

crossing of the positive edge 

of CK and negative edge of 

CKB. Output (read) data is 

referenced to the crossings of 

CK and CKB (both directions 

of crossing).