Intel C2518 FH8065501516710 Data Sheet

Product codes
FH8065501516710
Page of 746
Volume 3—Signal Names and Descriptions—C2000 Product Family
System DDR Memory Signals
Intel
®
 Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 3 of 3
September 2014
582
Order Number: 330061-002US
DDR3_1_ODT[3:0]
O
DDR
4
VDDR
DDR3 On-Die Termination 
Enable: (active high). ODT 
(registered HIGH) enables 
termination resistance 
internal to the DDR device 
SDRAM. When the ODT 
feature is enabled, it is 
dynamically enabled for the 
receiver of the data. The SoC 
does this internally for read 
data returning from the DRAM 
devices. For write data to the 
DRAM devices, the M_ODT[] 
pins are asserted to enable 
ODT within the DRAM devices 
themselves. Because ODT 
consumes power, when the 
feature is enabled, it is control 
dynamically by the SoC. ODT 
impacts the DQ, DQS, and DM 
signals. The ODT pin is 
ignored by the DDR devices if 
the EMR(1) is programmed to 
disable ODT. One pin per rank.
DDR3_1_RASB
O
DDR
1
VDDR
DDR3 Row Address Strobe: 
(active low). Used with CASB 
and RASB (along with CSB) to 
define commands. RAS, CAS, 
and WE (along with CS) define 
the command being entered.
DDR3_1_CASB
O
DDR
1
VDDR
DDR3 Column Address 
Strobe: (active low). Used 
with CAS#, RAS#, and CS# to 
define commands. RAS, CAS, 
and WE (along with CS) define 
the command being entered.
DDR3_1_WEB
O
DDR
1
VDDR
DDR3 Write Enable: (active 
low). Used with CAS#, RAS#, 
and CS# to define commands. 
RAS, CAS, and WE (along with 
CS) define the command 
being entered.
DDR3_1_DRAM_PWROK
I
DDR
1
VDDR
DRAM POWER OK. An active 
high signal indicates that the 
DDR PHY voltage (VDDR) is 
good.
DDR3_1_DRAMRSTB
O
DDR
1
VDDR
For resetting the DDR DIMMs.
DDR3_1_VCCA_PWROK
I
DDR
1
VDDR
DDR3 Indication to the DDRIO 
that the SoC core well voltage 
is valid. This is connected to 
the SoC input COREPWROK 
(except they are different 
voltages).
DDR3_1_VREF
I
DDR
1
100 1%, 
PD
VDDR
External Vref from the resistor 
divider on board.
DDR3_1_ODTPU
I/O
DDR
1
VDDR
DDR3 Compensation Pad. 
Board trace + External 
Precision resistor = 275. The 
resistor is pulled-down to 
VSS.
Table 31-5. DDR1 Signals (Sheet 4 of 5)
Signal Name
I/O 
Type
I/O Buffer 
Type
Ball 
Count
Internal 
Resistor 
PU/PD
External 
Resistor 
PU/PD
Power 
Rail
Description