Intel C2518 FH8065501516710 Data Sheet

Product codes
FH8065501516710
Page of 746
Volume 3—Signal Electrical and Timing Characteristics—C2000 Product Family
PCI Express Root Port Interface
Intel
®
 Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 3 of 3
September 2014
642
Order Number: 330061-002US
33.2
PCI Express Root Port Interface
The SoC has up to 16 PCI Express* ports depending on product SKU. Each port consists 
of a Transmitter differential pair and a Receiver differential pair which are in the 1.0-
Volt Core power well of the SoC.
• PCIE_TXP[15:0], PCIE_TXN[15:0] (Low Voltage Differential)
• PCIE_RXP[15:0], PCIE_RXN[15:0] (Low Voltage Differential)
See Section 4.3. Electrical Sub-Block of the PCI Express Base Specification, Revision 
2.1 for DC and AC timing specifications for the host Transmitter and Receiver channels. 
The SoC supports devices with 5.0 GT/s and 2.5 GT/s capabilities.
The SoC electrical requirements for the PCIe* differential reference clock inputs are in 
.
The SoC provides an integrated SMBus controller and interface that can be used in a 
PCI Express* interface design. The electrical characteristics are in 
The SoC provides a Platform Reset output signal pin, PMU_PLTRST_B, and a 
PMU_WAKE_B input signal pin that can be used by the platform board design to create 
the PCIe interface signals PERST# and WAKE# respectively. The electrical 
characteristics for these signals are in 
.
The SoC provides two general-purpose clock output pins from the SoC clock control 
unit. The signals are called FLEX_CLK_SE0 and FLEX_CLK_SE1. The electrical 
characteristics are in