Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 3 of 3

Order Number: 330061-002US

643

For GbE reference clock input specifications, see 

.

The SoC has up to four GbE ports depending on product SKU. Each port consists of a 

Transmitter differential pair and a Receiver differential pair which are in the 1.0-Volt 

SUS power well of the SoC.

• GBE_TXP[3:0], GBE_TXN[3:0] (Low Voltage Differential)
• GBE_RXP[3:0], GBE_RXN[3:0] (Low Voltage Differential)

The electrical specifications conform to standards and depend on the mode of 

operation:

• SGMII (MAC to PHY)
• 1000BASE-KX (1 GbE)
• 2500BASE-X (2.5 GbE)

The SoC is designed to support 1000BASE-T when an external, SGMII-capable Physical-

Layer device (PHY) is used in the platform board design. The SoC interface with the 

PHY conforms with the industry’s Serial Gigabit Media Independent Interface (SGMII) 

Specification. The specification is a modified Physical Coding Sublayer (PCS) layer of 

the Gigabit Media Independent Interface (GMII) of the IEEE Standard 802.3*-2008, 

SECTION THREE, Clause 36, type 1000BASE-X. Refer to Clause 36 as well as Clause 37 

of the IEEE 802.3 standard. The interface circuitry conforms to the IEEE Standard 

802.3*-2008, SECTION FIVE, Clause 70 - Physical Medium Dependent Sublayer and 

Baseband Medium, Type 1000BASE-KX. Refer to 70.7 1000BASE-KX electrical 

characteristics of Clause 70.

The SoC is designed to operate with Ethernet interface circuitry that conforms to of the 

IEEE Standard 802.3*-2008, Section 5, Clause 70 - Physical Medium Dependent 

Sublayer and Baseband Medium, Type 1000BASE-KX. Refer to 70.7 1000BASE-KX 

electrical characteristics of Clause 70.