Intel C2518 FH8065501516710 Data Sheet
Product codes
FH8065501516710
Intel
®
Atom™ Processor C2000 Product Family for Microserver
September 2014
Datasheet, Vol. 3 of 3
Order Number: 330061-002US
651
Volume 3—Signal Electrical and Timing Characteristics—C2000 Product Family
2.5 and 1 Gigabit Ethernet (GbE) Interface
33.3.3.2
Receiver Characteristics
Receiver characteristics at TP4 are summarized in
and detailed in
through
33.3.3.2.1
Receiver Interference Tolerance
The receiver interference tolerance shall be measured as described in Annex 69A -
Interference Tolerance Testing of the IEEE Standard 802.3*-2008, with the parameters
. The data pattern for the interference tolerance test shall be the
continuous jitter test pattern as defined in 48A.5 in Annex 48A - Jitter Test Patterns of
IEEE Standard 802.3*-2008. The receiver shall satisfy the requirements for
interference tolerance specified in Annex 69A.
Table 33-8. Receiver Characteristics
Parameter
Refer to
Value
Units
Bit error ratio
10
–12
Signaling speed, per lane
3.125 ± 100 ppm
GBd
Unit interval (UI) nominal
320
ps
Receiver coupling
AC
Differential input peak-to-peak amplitude (maximum)
1600
mV
Differential input return loss
1
(minimum)
1. Relative to 100 Ω differential.
See the two equations
in
.
dB
Table 33-9. Interference Tolerance Parameters
Parameter
Value
Units
Target BER
10
–12
m
TC
1
(min.)
1. m
TC
is defined in Equation 69A–6 of Annex 69A in the IEEE Standard 802.3*-2008.
1.0
Amplitude of broadband noise (min. RMS)
8.1
mV
Applied transition time (20%–80%, min.)
130
ps
Applied sinusoidal jitter (min. peak-to-peak)
0.17
UI
Applied random jitter (min. peak-to-peak)
2
2. Applied random jitter is specified at a BER of 10
–12
.
0.18
UI
Applied duty cycle distortion (min. peak-to-peak)
0.0
UI