Intel C2518 FH8065501516710 Data Sheet

Product codes
FH8065501516710
Page of 746
Volume 2—System Agent and Root Complex—C2000 Product Family
Root Complex
Intel
®
 Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 2 of 3
September 2014
66
Order Number: 330061-002US
4.4.2
Root Complex Primary Transaction Routing
The root complex provides primary transaction routing utilizing positive and negative 
decode. Positive decode routing is based on matching attributes between the 
internally-routed transaction and the attached root complex agents. The root complex 
has internal knowledge of its attached agent attributes to enable this decode.
Internal transaction routing is shown in 
Table 4-3
. Transactions not listed in this table 
cause a negative decode. These negative-decode transaction include:
• Lock transaction
• I/O space transaction other than to a root port aperture
• Message transaction with a downstream destination
• Unsupported source-destination pair
• Transaction to disabled memory or I/O region
• Unrecognized transaction type
• Unrecognized address
• Unrecognized ID
The SoC Negative Decode Handler (NDH) mentioned in 
Table 4-3
 sends an 
Unsupported Request (UR) completion on reads and drops writes and completions. 
NDH event error logging occurs.
Table 4-3.
Root Complex Primary Transaction Routing
Transaction
Type
Decode
Type
Source
Destination
Memory Space
Base Address Register (BAR)
Any
PCIe* Root Ports
Aperture in Memory Space
Any
PCIe Root Ports
Refetchable Aperture
Any
PCIe Root Ports
Message Signalled Interrupt 
(MSI)
Any
SoC System Agent
HMBound Address
Any
SoC System Agent
Address in the DOS Region
Any
SoC System Agent
I/O Space
Aperture in I/O Space
Any
PCIe Root Ports
Configuration 
Space
Type 0
SoC System Agent PCIe Root Ports, Integrated devices
Type 1 (Bridge)
SoC System Agent PCIe Root Ports
Completion
ID Route
Any
PCIe Root Ports, SoC System Agent
Any
Negative Decode
Any
Integrated Devices
not the PCIe Root Port controllers
Note:
Negative-decode 
transactions that have 
characteristics not capable of 
the integrated devices, such 
as an address width greater 
than 36 bits, or a payload of 
more than 64 bytes, are 
instead sent to the SoC 
Negative Decode Handler 
(NDH).