Intel C2518 FH8065501516710 Data Sheet
Product codes
FH8065501516710
Volume 3—Signal Electrical and Timing Characteristics—C2000 Product Family
SoC JTAG and Debug Interfaces
Intel
®
Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 3 of 3
September 2014
686
Order Number: 330061-002US
33.23.2
Interface Timing Parameters and Waveforms
and
contain the timing specifications for the JTAG and Debug
signals. Unless otherwise noted, all specifications in these tables apply to all SoC
frequencies and a maximum platform-board JTAG-signal skew of ±500 ps. Parameters
are not 100% tested and are specified by design characterization.
Notes:
1.
40% of one-half of T
P
(CLK Period).
2.
It is recommended that TMS be asserted while TRST_B is being de-asserted.
Table 33-49. JTAG Signal Timing Specifications
Symbol
Parameter
Min
Max
Units
Figure
Notes
T
P
TCK Period
15
–
ns
66 MHz
T
CL
TCK Clock Low Time
0.2 * T
P
–
ns
1
T
CH
TCK Clock High Time
0.2 * T
P
–
ns
1
T
S
TDI, TMS Setup Time
11
–
ns
T
H
TDI, TMS Hold Time
5
–
ns
T
VAL
TCK falling to TDO output valid
–
11
ns
T
OFF
TCK falling to TDO output high
impedance
–
11
ns
T
W
TRST_B assert time
2
–
ns
2