Intel C2350 FH8065401488914 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 2 of 3

September 2014

78

Order Number: 330061-002US

IA32_MCi_CTL

In general, the IA32_MCi_CTL registers function in a similar fashion. Each is a 

64-bit, read/write MSR. Each bit of the 64-bit register can be set by the software to 

enable or disable an individual error-reporting condition.
The SoC cores do not alias IA32_MC0_CTL to the EBL_CR_POWERON (MSR 2Ah).
The BIOS sets this register in all six banks to all ones (FFFF_FFFF_FFFF_FFFFh) 

even though some bits are unused and are not error-enable bits. Even so, when the 

software reads bits that correspond to unimplemented error conditions, a zero is 

always returned. The setting of this register does not affect the logging of errors 

but only the reporting of exceptions for uncorrectable errors. The errors are always 

logged.

IA32_MCi_STATUS

The IA32_MCi_STATUS registers contain information related to a machine check 

error if the VAL bit (bit 63 of the particular IA32_MCi_STATUS register) is set. 

These registers follow a general format shown in Volume 3, Chapter 15 of the 

 64 and IA-32 Architectures Software Developer’s Manual. The software 

clears this MSR by explicitly writing 0 to it. Writing any other value causes a general 

protection exception. As mentioned previously, this register is not reset by the 

hardware and retains the prior values across warm resets. Refer to the 

IA32_MCi_STATUS descriptions for each bank in the following subsections.

IA32_MCi_ADDR

If implemented by the bank, the 64-bit IA32_MCi_ADDR register contains the 

address of the code or data memory location that produced the machine check 

error if the ADDRV flag (bit 58) in the IA32_MCi_STATUS register is set. This 

register must not be read if the corresponding ADDRV flag is not set. This register 

is updated according to the same rules regarding the overwriting of errors in the 

corresponding IA32_MCi_STATUS register. Writing anything but 0 to an 

implemented IA32_MCi_ADDR MSR causes a general protection exception. Like the 

IA32_MCi_STATUS register, IA32_MCi_ADDR is not reset by the hardware and 

retains the prior values across warm resets.
For MC1 (bank 1, BIU), a read or write to MSR 406h causes a general protection 

exception.

IA32_MCi_MISC and IA32_MCi_CTL2

These machine check MSRs are not implemented in the SoC. A read or write to 

these MSRs causes a general protection exception.

The six machine check error-reporting banks for the SoC are described in the following 

subsections.

Machine check error reporting for the Bus Interface Unit (BIU) associated with the 

particular core uses two machine check banks: MC0 and MC1. The MC0 bank is 

described first.

This document does not provide details of the individual Error-Reporting Enable flags of 

the 64-bit IA32_MC0_CTL register. Refer to the general description of “IA32_MCi_CTL.”