Intel Core 2 Duo E7300 BX80570E7300 User Manual

Thermal and Mechanical Design Guidelines   

 39 

The processor uses the Digital Thermal Sensor (DTS) as the on-die sensor to use for 

fan speed control (FSC).  The DTS is monitoring the same sensor that activates the 
TCC (see Section 

4.2.2). Readings from the DTS are relative to the activation of the 

TCC. The DTS value where TCC activation occurs is 0 (zero). 

A T

CONTROL

 value will be provided for use with DTS. The usage model for T

CONTROL

 with 

the DTS as below: 

  If the Digital thermal sensor reading is less than T

CONTROL, 

the fan speed can be 

reduced. 

  If the Digital thermal sensor reading is greater than or equal to T

CONTROL, 

then T

C

 

must be maintained at or below the Thermal Profile for the measured power 

dissipation. 

The DTS T

CONTROL

 value is factory configured and is written into T

OFFSET

 MSR, the BIOS 

can read the T

OFFSET

 MSR and provide this value to the fan speed control device. 

 

 

Note:  The processor has only DTS and no thermal diode. The T

CONTROL 

in the MSR is relevant 

only to the DTS. 

The PECI interface is a proprietary single wire bus between the processor and the 

chipset or other health monitoring device. At this time the digital thermal sensor is the 

only data being transmitted. For an overview of the PECI interface see PECI Feature 

Set Overview. For additional information on the PECI see the datasheet.  

The PECI bus is available on pin G5 of the LGA 775 socket. Intel chipsets beginning 

with the ICH8 have included PECI host controller. The PECI interface and the 

Manageability Engine are key elements to the Intel