Intel E3845 FH8065301487715 Data Sheet

Intel

Product codes

FH8065301487715

Intel

®

Atom™ Processor E3800 Product Family

Datasheet

3615

C4–C7h

4

“Linked List Pointer Register for Channel 2 - High (LLP2_HI)—Offset C4h” on

00000000h

C8–CBh

4

“Control Register for Channel 2 - Low (CTL2_LO)—Offset C8h” on page 3652

00304801h

CC–CFh

4

“Control Register for Channel 2 - High (CTL2_HI)—Offset CCh” on page 3653

00000002h

D0–D3h

4

“Source Status Register for Channel 2 - Low (SSTAT2_LO)—Offset D0h” on

00000000h

D4–D7h

4

“Source Status Register for Channel 2 - High (SSTAT2_HI)—Offset D4h” on

00000000h

D8–DBh

4

“Dest Status Register for Channel 2 - Low (DSTAT2_LO)—Offset D8h” on

00000000h

DC–DFh

4

“Dest Status Register for Channel 2 - High (DSTAT2_HI)—Offset DCh” on

00000000h

E0–E3h

4

“Source Status Address Register for Channel 2 - Low (SSTATAR2_LO)—Offset

E0h” on page 3656

00000000h

E4–E7h

4

“Source Status Address Register for Channel 2 - High (SSTATAR2_HI)—Offset

E4h” on page 3656

00000000h

E8–EBh

4

“Dest Status Address Register for Channel 2 - Low (DSTATAR2_LO)—Offset E8h”

00000000h

EC–EFh

4

“Dest Status Address Register for Channel 2 - High (DSTATAR2_HI)—Offset

ECh” on page 3657

00000000h

F0–F3h

4

“Configuration Register for Channel 2 - Low (CFG2_LO)—Offset F0h” on

00000E40h

F4–F7h

4

“Configuration Register for Channel 2 - High (CFG2_HI)—Offset F4h” on

00000004h

F8–FBh

4

“Source Gather Register for Channel 2 - Low (SGR2_LO)—Offset F8h” on

00000000h

FC–FFh

4

“Source Gather Register for Channel 2 - High (SGR2_HI)—Offset FCh” on

00000000h

100–103h

4

“Destination Scatter Register for Channel 2 - Low (DSR2_LO)—Offset 100h” on

00000000h

104–107h

4

“Dest Scatter Register for Channel 2 - High (DSR2_HI)—Offset 104h” on

00000000h

108–10Bh

4

“Source Address Register for Channel 3 - Low (SAR3_LO)—Offset 108h” on

00000000h

10C–10Fh

4

“Source Address Register for Channel 3 - High (SAR3_HI)—Offset 10Ch” on

00000000h

110–113h

4

“Destination Address Register for Channel 3 - Low (DAR3_LO)—Offset 110h” on

00000000h

114–117h

4

“Destination Address Register for Channel 3 - High (DAR3_HI)—Offset 114h” on

00000000h

118–11Bh

4

“Linked List Pointer Register for Channel 3 - Low (LLP3_LO)—Offset 118h” on

00000000h

11C–11Fh

4

“Linked List Pointer Register for Channel 3 - High (LLP3_HI)—Offset 11Ch” on

00000000h

120–123h

4

“Control Register for Channel 3 - Low (CTL3_LO)—Offset 120h” on page 3665

00304801h

124–127h

4

“Control Register for Channel 3 - High (CTL3_HI)—Offset 124h” on page 3666

00000002h

128–12Bh

4

“Source Status Register for Channel 3 - Low (SSTAT3_LO)—Offset 128h” on

00000000h

Table 253.

Summary of SIO DMA 2 Memory Mapped I/O Registers—BAR (Continued)

Offset

Size

(Bytes)

Register Name (Register Symbol)

Default

Value