Intel E3845 FH8065301487715 Data Sheet

Intel

Product codes

FH8065301487715

Intel

®

Atom™ Processor E3800 Product Family

Datasheet

3617

190–193h

4

“Source Status Address Register for Channel 4 - Low (SSTATAR4_LO)—Offset

190h” on page 3682

00000000h

194–197h

4

“Source Status Address Register for Channel 4 - High (SSTATAR4_HI)—Offset

194h” on page 3682

00000000h

198–19Bh

4

“Dest Status Address Register for Channel 4 - Low (DSTATAR4_LO)—Offset

198h” on page 3683

00000000h

19C–19Fh

4

“Dest Status Address Register for Channel 4 - High (DSTATAR4_HI)—Offset

19Ch” on page 3683

00000000h

1A0–1A3h

4

“Configuration Register for Channel 4 - Low (CFG4_LO)—Offset 1A0h” on

00000E80h

1A4–1A7h

4

“Configuration Register for Channel 4 - High (CFG4_HI)—Offset 1A4h” on

00000004h

1A8–1ABh

4

“Source Gather Register for Channel 4 - Low (SGR4_LO)—Offset 1A8h” on

00000000h

1AC–1AFh

4

“Source Gather Register for Channel 4 - High (SGR4_HI)—Offset 1ACh” on

00000000h

1B0–1B3h

4

“Destination Scatter Register for Channel 4 - Low (DSR4_LO)—Offset 1B0h” on

00000000h

1B4–1B7h

4

“Dest Scatter Register for Channel 4 - High (DSR4_HI)—Offset 1B4h” on

00000000h

1B8–1BBh

4

“Source Address Register for Channel 5 - Low (SAR5_LO)—Offset 1B8h” on

00000000h

1BC–1BFh

4

“Source Address Register for Channel 5 - High (SAR5_HI)—Offset 1BCh” on

00000000h

1C0–1C3h

4

“Destination Address Register for Channel 5 - Low (DAR5_LO)—Offset 1C0h” on

00000000h

1C4–1C7h

4

“Destination Address Register for Channel 5 - High (DAR5_HI)—Offset 1C4h” on

00000000h

1C8–1CBh

4

“Linked List Pointer Register for Channel 5 - Low (LLP5_LO)—Offset 1C8h” on

00000000h

1CC–1CFh

4

“Linked List Pointer Register for Channel 5 - High (LLP5_HI)—Offset 1CCh” on

00000000h

1D0–1D3h

4

“Control Register for Channel 5 - Low (CTL5_LO)—Offset 1D0h” on page 3691

00304801h

1D4–1D7h

4

“Control Register for Channel 5 - High (CTL5_HI)—Offset 1D4h” on page 3692

00000002h

1D8–1DBh

4

“Source Status Register for Channel 5 - Low (SSTAT5_LO)—Offset 1D8h” on

00000000h

1DC–1DFh

4

“Source Status Register for Channel 5 - High (SSTAT5_HI)—Offset 1DCh” on

00000000h

1E0–1E3h

4

“Dest Status Register for Channel 5 - Low (DSTAT5_LO)—Offset 1E0h” on

00000000h

1E4–1E7h

4

“Dest Status Register for Channel 5 - High (DSTAT5_HI)—Offset 1E4h” on

00000000h

1E8–1EBh

4

“Source Status Address Register for Channel 5 - Low (SSTATAR5_LO)—Offset

1E8h” on page 3695

00000000h

1EC–1EFh

4

“Source Status Address Register for Channel 5 - High (SSTATAR5_HI)—Offset

1ECh” on page 3695

00000000h

1F0–1F3h

4

“Dest Status Address Register for Channel 5 - Low (DSTATAR5_LO)—Offset

1F0h” on page 3696

00000000h

Table 253.

Summary of SIO DMA 2 Memory Mapped I/O Registers—BAR (Continued)

Offset

Size

(Bytes)

Register Name (Register Symbol)

Default

Value