Intel E3845 FH8065301487715 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

4429

The SoC provides a System Management Bus (SMBus) 2.0 host controller. The host 
controller provides a mechanism for the processor to initiate communications with 
SMBus peripherals (slaves). The SoC is also capable of operating in a mode in which it 
can communicate with I

2

C compatible devices.

The SoC can perform SMBus messages with packet error checking (PEC) enabled or 
disabled. The actual PEC calculation and checking can be performed in either hardware 
or software.

The SMBus Address Resolution Protocol (ARP) is supported by using the existing host 
controller commands through software, except for the Host Notify command (which is 
actually a received message).

The programming model of the host controller is combined into two portions: a PCI 
configuration portion, and a system I/O mapped portion. All static configuration, such 
as the I/O base address, is done using the PCI configuration space. Real-time 
programming of the Host interface is done in system I/O space.

Please see 

 for additional details.

The signal description table has the following headings:

•

Signal Name: The name of the signal/pin

•

Direction: The buffer direction can be either input, output, or I/O (bidirectional)

•

Platform Power: The reference power plane.

•

Description: A brief explanation of the signal’s function

I

O

I

O

I

O

I

O

I

O

I

O

I

O

O

Platform Control Unit

UART

SMB

iLB

SPI

PM
C