Intel E3845 FH8065301487715 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

4430

Datasheet

The SMBus host controller is used to send commands to other SMBus slave devices. 
Software sets up the host controller with an address, command, and, for writes, data 
and optional PEC; and then tells the controller to start. When the controller has finished 
transmitting data on writes, or receiving data on reads, it generates an SMI# or 
interrupt, if enabled.

The host controller supports 8 command protocols of the SMBus interface (see System 
Management Bus (SMBus) Specification, Version 2.0): Quick Command, Send Byte, 
Receive Byte, Write Byte/Word, Read Byte/Word, Process Call, Block Read/Write and 
Block Write–Block Read Process Call. Additionally, it supports 1 command protocol for 
I

2

C devices: I

2

C Read.

The SMBus host controller requires that the various data and command fields be setup 
for the type of command to be sent. When software sets the START bit, the SMBus Host 
controller performs the requested transaction, and interrupts the processor (or 
generates an SMI#) when the transaction is completed. Once a START command has 
been issued, the values of the “active registers” (Host Control (SMB_Mem_HCTL), Host 
Command (SMB_Mem_HCMD), Transmit Slave Address (SMB_Mem_TSA), Data 0 
(SMB_Mem_HD0), Data 1 (SMB_Mem_HD1)) should not be changed or read until the 
interrupt status message (SMB_Mem_HSTS.INTR) has been set (indicating the 
completion of the command). Any register values needed for computation purposes 
should be saved prior to issuing of a new command, as the SMBus host controller 
updates all registers while completing the new command.

In all of the following commands, the Host Status (SMB_Mem_HSTS) register is used to 
determine the progress of the command. While the command is in operation, the 
SMB_Mem_HSTS.HBSY bit is set. If the command completes successfully, the 
SMB_Mem_HSTS.INTR bit will be set. If the device does not respond with an 

I/OD

V1P8S

SMBus Alert: This signal is used to generate internal 
SMI#.
This signal is muxed and may be used by other functions.

I/OD

V1P8S

SMBus Clock: External pull-up resistor is required.
This signal is muxed and may be used by other functions.

I/OD

V1P8S

SMBus Data: External pull-up resistor is required.
This signal is muxed and may be used by other functions.