Intel E3845 FH8065301487715 Data Sheet
Product codes
FH8065301487715
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
4565
38.5.2
GCFG (HPET_GCFG)—Offset FED00010h
General Configuration
Access Method
Default: 0000000000000000h
38.5.3
GIS (HPET_GIS)—Offset FED00020h
General Interrupt Status
Access Method
Default: 0000000000000000h
12:8
02h
RO
NT:
Number of Timers (NT): Indicates that 3 timers are supported.
7:0
01h
RO
RID:
Revision ID (RID): Indicates that revision 1.0 of the specification is implemented.
Bit
Range
Default &
Access
Description
Type:
Memory Mapped I/O Register
(Size: 64 bits)
HPET_GCFG:
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RE
SERV
ED
LRE EN
Bit
Range
Default &
Access
Description
63:2
0b
RO
RESERVED:
Reserved.
1
0b
RW
LRE:
Legacy Rout Enable (LRE): When set, interrupts will be routed as follows: Timer 0
will be routed to IRQ0 in 8259 or IRQ2 in the I/O APIC Timer 1 will be routed to IRQ8 in
8259 and I/O APIC Timer 2 will be routed as per the routing in T2C When set, the
T[1:0]C.IR will have no impact for timers 0 and 1.
0
0b
RW
EN:
Overall Enable (EN): When set, the timers can generate interrupts. When cleared,
the main counter will halt and no interrupts will be caused by any timer. For level-
triggered interrupts, if an interrupt is pending when this bit is cleared, the GIS.Tx will
not be cleared.
Type:
Memory Mapped I/O Register
(Size: 64 bits)
HPET_GIS:
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESE
RVE
D
T2 T1 T0