Intel E3845 FH8065301487715 Data Sheet
Product codes
FH8065301487715
Intel
®
Atom™ Processor E3800 Product Family
4566
Datasheet
38.5.4
MCV (HPET_MCV)—Offset FED000F0h
Main Counter Value
Access Method
Default: 0000000000000000h
38.5.5
T0C (HPET_T0C)—Offset FED00100h
Timer 0 Config and Capabilities
Access Method
Default: 00F0000000000030h
Bit
Range
Default &
Access
Description
63:3
0b
RO
RESERVED:
Reserved.
2
0b
RW
T2:
Timer 2 Status (T2): Same functionality as T0, for timer 2.
1
0b
RW
T1:
Timer 1 Status (T1): Same functionality as T0, for timer 1.
0
0b
RW
T0:
Timer 0 Status (T0): In edge triggered mode, this bit always reads as 0. In level
triggered mode, this bit is set when an interrupt is active.
Type:
Memory Mapped I/O Register
(Size: 64 bits)
HPET_MCV:
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CV
Bit
Range
Default &
Access
Description
63:0
0b
RW
CV:
Counter Value (CV): Reads return the current value of the counter. Writes load the
new value to the counter. Timers 1 and 2 return 0 for the upper 32-bits of this register.
Type:
Memory Mapped I/O Register
(Size: 64 bits)
HPET_T0C:
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8
4
0
0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0
CV
RE
SER
V
ED
FID FE
IR
T32M
RE
SE
RVED
2
TVS
TS PIC TY
P IE IT
RE
SE
RVED
3
Bit
Range
Default &
Access
Description
63:32
00f00000h
RO
IRC (CV):
Interrupt Rout Capability (IRC): Indicates I/OxAPIC interrupts the timer can
use: Timer 0,1: 00f00000h. Indicates support for IRQ20, 21, 22, 23 Timer 2:
00f00800h. Indicates support for IRQ11, 20, 21, 22, and 23