Intel E3845 FH8065301487715 Data Sheet
Product codes
FH8065301487715
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
4569
38.5.9
T1CV (HPET_T1CV)—Offset FED00128h
Timer 1 Comperator Value
Access Method
Default: 00000000FFFFFFFFh
14
0b
RO
FE:
FSB Enable (FE): Not supported, since FID is not supported.
13:9
0b
RW
IR:
Interrupt Rout (IR): Indicates the routing for the interrupt to the IOxAPIC. If the
value is not supported by this prarticular timer, the value read back will not match what
is written. If GCFG.LRE is set, then Timers 0 and 1 have a fixed routing, and this field
has no effect.
8
0b
RO
T32M:
Timer 32-bit Mode (T32M): When set, this bit forces a 64-bit timer to behave as
a 32-bit timer. For timer 0, this bit will be read/write and default to 0. For timers 1 and
2, this bit is read only '0'.
7
0b
RO
RESERVED (RESERVED2):
Timer 32-bit Mode (T32M): When set, this bit forces a 64-
bit timer to behave as a 32-bit timer. For timer 0, this bit will be read/write and default
to 0. For timers 1 and 2, this bit is read only '0'.
6
0b
RO
TVS:
Timer Value Set (TVS): This bit will return 0 when read. Writes will only have an
effect for Timer 0 if it is set to periodic mode. Writes will have no effect for Timers 1 and
2.
5
0b
RO
TS:
Timer Size (TS): 1 = 64-bits, 0 = 32-bits. Set for timer 0. Cleared for timers 1 and
2.
4
0b
RO
PIC:
Periodic Interrupt Capable (PIC): When set, hardware supports a periodic mode for
this timer's interrupt. This bit is set for timer 0, and cleared for timers 1 and 2.
3
0b
RO
TYP:
Timer Type (TYP): If PIC is set, this bit is read/write, and can be used to enable
the timer to generate a periodic interrupt. This bit is RW for timer 0, and RO for timers 1
and 2.
2
0b
RW
IE:
Interrupt Enable (IE): When set, enables the timer to cause an interrupt when it
times out. When cleared, the timer count and generates status bits, but will not cause
an interrupt.
1
0b
RW
IT:
Timer Interrupt Type (IT): When cleared, interrupt is edge triggered. When set,
interrupt is level triggered and will be held active until it is cleared by writing 1 to
GIS.Tn. If another interrupt occurs before the interrupt is cleared, the interrupt remains
active.
0
0b
RO
RESERVED (RESERVED3):
Reserved.
Bit
Range
Default &
Access
Description
Type:
Memory Mapped I/O Register
(Size: 64 bits)
HPET_T1CV:
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
RE
SERV
ED1
T1CV