Intel E3845 FH8065301487715 Data Sheet
Product codes
FH8065301487715
Intel
®
Atom™ Processor E3800 Product Family
4570
Datasheet
38.5.10
T2C (HPET_T2C)—Offset FED00140h
Timer 2 Config and Capabilities
Access Method
Default: 00F0080000000000h
Bit
Range
Default &
Access
Description
63:32
0b
RO
RESERVED (RESERVED1):
Reserved.
31:0
FFFFFFFFh
RO
T1CV:
Timer 1 Comperator Value
Type:
Memory Mapped I/O Register
(Size: 64 bits)
HPET_T2C:
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8
4
0
0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CV
RE
SERV
ED
FID FE
IR
T3
2
M
RE
SERV
ED2 TV
S
TS PIC TY
P IE IT
RE
SERV
ED3
Bit
Range
Default &
Access
Description
63:32
00f00800h
RO
IRC (CV):
Interrupt Rout Capability (IRC): Indicates I/OxAPIC interrupts the timer can
use: Timer 0,1: 00f00000h. Indicates support for IRQ20, 21, 22, 23 Timer 2:
00f00800h. Indicates support for IRQ11, 20, 21, 22, and 23
31:16
0h
RO
RESERVED:
Reserved.
15
0b
RO
FID:
FSB Interrupt Delivery (FID): Not supported
14
0b
RO
FE:
FSB Enable (FE): Not supported, since FID is not supported.
13:9
0b
RW
IR:
Interrupt Rout (IR): Indicates the routing for the interrupt to the IOxAPIC. If the
value is not supported by this prarticular timer, the value read back will not match what
is written. If GCFG.LRE is set, then Timers 0 and 1 have a fixed routing, and this field
has no effect.
8
0b
RO
T32M:
Timer 32-bit Mode (T32M): When set, this bit forces a 64-bit timer to behave as
a 32-bit timer. For timer 0, this bit will be read/write and default to 0. For timers 1 and
2, this bit is read only '0'.
7
0b
RO
RESERVED (RESERVED2):
Timer 32-bit Mode (T32M): When set, this bit forces a 64-
bit timer to behave as a 32-bit timer. For timer 0, this bit will be read/write and default
to 0. For timers 1 and 2, this bit is read only '0'.
6
0b
RO
TVS:
Timer Value Set (TVS): This bit will return 0 when read. Writes will only have an
effect for Timer 0 if it is set to periodic mode. Writes will have no effect for Timers 1 and
2.
5
0b
RO
TS:
Timer Size (TS): 1 = 64-bits, 0 = 32-bits. Set for timer 0. Cleared for timers 1 and
2.
4
0b
RO
PIC:
Periodic Interrupt Capable (PIC): When set, hardware supports a periodic mode for
this timer's interrupt. This bit is set for timer 0, and cleared for timers 1 and 2.