Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

276

Datasheet

O

Analog

Resistor Compensation: This signal needs to be 
terminated to VSS on board (refer to platform design 
guide for resistor value). This external resistor 
termination scheme is used for Resistor compensation 
of DRAM ODT strength.

O

Analog

Resistor Compensation: This signal needs to be 
terminated to VSS on board (refer to platform design 
guide for resistor value). This external resistor 
termination scheme is used for Resistor compensation 
of DQ buffers

O

Analog

Resistor Compensation: This signal needs to be 
terminated to VSS on board (refer to platform design 
guide for resistor value). This external resistor 
termination scheme is used for Resistor compensation 
of CMD buffers.

I

Analog

Reference Voltage: DRAM interface Reference 
Voltage

I

Asynchro

nous 

CMOS

Core Power OK: This signal indicates the status of the 
DRAM Core power supply (power on in S0).

I

Asynchro

nous 

CMOS

VDD Power OK: Asserted once the VRM is settled. 
Used primarily in the DRAM PHY to determine S3 state.

O

DRAM Reset: This signal is used to reset DRAM 
devices.

I/O

Pull-down to VSS through an 100kOhm 1% resistor.

O

DDR3

SDRAM and inverted Differential Clock: (1 pair per 
Rank)
The differential clock pair is used to latch the command 
into DRAM. Each pair corresponds to one rank on DRAM 
side.

O

DDR3

Chip Select: (1 per Rank). Used to qualify the command 
on the command bus for a particular rank.

O

DDR3

Clock Enable: (power management)
It is used during DRAM power up/power down and Self 
refresh. 
Note: DDR3L uses only DRAM1_CKE[0,2]. 
DRAM1_CKE[1,3] are not being used for DDR3L.