Intel E3815 FH8065301567411 Hoja De Datos
Los códigos de productos
FH8065301567411
System Memory Controller
Intel
®
Atom™ Processor E3800 Product Family
276
Datasheet
DRAM_RCOMP[2]
O
Analog
Resistor Compensation: This signal needs to be
terminated to VSS on board (refer to platform design
guide for resistor value). This external resistor
termination scheme is used for Resistor compensation
of DRAM ODT strength.
terminated to VSS on board (refer to platform design
guide for resistor value). This external resistor
termination scheme is used for Resistor compensation
of DRAM ODT strength.
DRAM_RCOMP[1]
O
Analog
Resistor Compensation: This signal needs to be
terminated to VSS on board (refer to platform design
guide for resistor value). This external resistor
termination scheme is used for Resistor compensation
of DQ buffers
terminated to VSS on board (refer to platform design
guide for resistor value). This external resistor
termination scheme is used for Resistor compensation
of DQ buffers
DRAM_RCOMP[0]
O
Analog
Resistor Compensation: This signal needs to be
terminated to VSS on board (refer to platform design
guide for resistor value). This external resistor
termination scheme is used for Resistor compensation
of CMD buffers.
terminated to VSS on board (refer to platform design
guide for resistor value). This external resistor
termination scheme is used for Resistor compensation
of CMD buffers.
DRAM_VREF
I
Analog
Reference Voltage: DRAM interface Reference
Voltage
Voltage
DRAM_CORE_PWROK
I
Asynchro
nous
CMOS
Core Power OK: This signal indicates the status of the
DRAM Core power supply (power on in S0).
DRAM Core power supply (power on in S0).
DRAM_VDD_S4_PWR
OK
OK
I
Asynchro
nous
CMOS
VDD Power OK: Asserted once the VRM is settled.
Used primarily in the DRAM PHY to determine S3 state.
Used primarily in the DRAM PHY to determine S3 state.
DRAM0_DRAMRST#
O
DRAM Reset: This signal is used to reset DRAM
devices.
devices.
ICLK_DRAM_TERM
[1:0]
[1:0]
I/O
Pull-down to VSS through an 100kOhm 1% resistor.
Table 150. Memory Channel 1 DDR3L Signals (Sheet 1 of 2)
Signal Name
Direction
Type
Description
DRAM1_CKP[2,0]
DRAM1_CKN[2,0]
O
DDR3
SDRAM and inverted Differential Clock: (1 pair per
Rank)
The differential clock pair is used to latch the command
into DRAM. Each pair corresponds to one rank on DRAM
side.
Rank)
The differential clock pair is used to latch the command
into DRAM. Each pair corresponds to one rank on DRAM
side.
DRAM1_CS[2,0]#
O
DDR3
Chip Select: (1 per Rank). Used to qualify the command
on the command bus for a particular rank.
on the command bus for a particular rank.
DRAM1_CKE[2,0]
O
DDR3
Clock Enable: (power management)
It is used during DRAM power up/power down and Self
refresh.
Note: DDR3L uses only DRAM1_CKE[0,2].
DRAM1_CKE[1,3] are not being used for DDR3L.
It is used during DRAM power up/power down and Self
refresh.
Note: DDR3L uses only DRAM1_CKE[0,2].
DRAM1_CKE[1,3] are not being used for DDR3L.
Table 149. Memory Channel 0 DDR3L Signals (Sheet 2 of 2)
Signal Name
Direction
Type
Description