Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
3034
Datasheet
21.15.134 reg_FIFO_PARTITION1_LO_type (FifoPartition1_LO)—Offset
408h
Access Method
Default: 00000000h
21.15.135 reg_FIFO_PARTITION1_HI_type (FifoPartition1_HI)—Offset
40Ch
Access Method
Default: 00000000h
12:0
0h
RW
PSIZE_CH_2:
Partition Byte Size assigned to Channel 2. Ranges from 0 Bytes to (2^13
- 1)=8191 Bytes. However, size needs to be DW Aligned, i.e. a multiple of 4.
Bit
Range
Default &
Access
Description
Type:
Memory Mapped I/O Register
(Size: 32 bits)
FifoPartition1_LO:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:21, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSV
D
2
PS
IZE
_
CH
_5
PS
IZE
_
CH
_4
Bit
Range
Default &
Access
Description
31:26
0h
RO
RSVD2:
Reserved
25:13
0h
RW
PSIZE_CH_5:
Partition Byte Size assigned to Channel 5. Ranges from 0 Bytes to (2^13
- 1)=8191 Bytes. However, size needs to be DW Aligned, i.e. a multiple of 4.
12:0
0h
RW
PSIZE_CH_4:
Partition Byte Size assigned to Channel 4. Ranges from 0 Bytes to (2^13
- 1)=8191 Bytes. However, size needs to be DW Aligned, i.e. a multiple of 4.
Type:
Memory Mapped I/O Register
(Size: 32 bits)
FifoPartition1_HI:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:21, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RS
VD1
PS
IZ
E_
C
H
_
7
PS
IZ
E_
C
H
_
6