Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
3175
22.3.29
SATT_BIOS_SIZE—Offset C8h
SEC Address Translation Table Entry no. 2 SAP Address space Size register, used by the
BIOS to configure the paging IMR related entry. Register acces control: FW=RO
PMC=RO Host=RW
Access Method
Default: 00000000h
22.3.30
SATT_TPM_CTRL (SATT_TPM_CTRL)—Offset D0h
SEC Address Translation Table Entry no. 4 control register, used by the BIOS to
configure the paging IMR related entry. Register acces control: FW=RO PMC=RO
Host=RW
Access Method
Default: 00001008h
Type:
PCI Configuration Register
(Size: 32 bits)
Offset:
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R
SVD_31_25
SA
P_S
IZE
Bit
Range
Default &
Access
Field Name (ID): Description
31:25
0b
NA
RESERVED (RSVD_31_25):
RESERVED BITS
24:0
X
RW
SAP_SIZE:
The SAP-address space size that defines the address space to be translated
using current SATT entry. This field is locked when SATT1_CTRL.ENTRY_VLD is set. Entry
hit condition is: ENTRY_VLD and SAP_BA (= SAPAddr[+SAPSize] ( SAP_BA + SAP_SIZE
Locked by entry_valid bit in SATT1_CTRL register
Type:
PCI Configuration Register
(Size: 32 bits)
Offset:
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0
RSVD_31_14
SE
C_T
P
M_DIS
A
BLE
D
BR
G_H
O
ST
_EN
BR
G_BA
_M
S
B
RSVD_7_4
TA
R
G
E
T
VA
LI
D
Bit
Range
Default &
Access
Field Name (ID): Description
31:14
0b
NA
RESERVED (RSVD_31_14):
RESERVED BITS