Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

3176

Datasheet

SEC Address Translation Table Entry no. 4 SAP Address space Size register, used by the 

BIOS to configure the paging IMR related entry. Register acces control: FW=RO 

PMC=RO Host=RW

Default: 00000000h

SEC Address Translation Table Entry no. 4 SAP Address space Size register, used by the 

BIOS to configure the paging IMR related entry. Register acces control: FW=RO 

PMC=RO Host=RW

Default: 00000000h

13

X

RO

Indicates to the BIOS that the fTPM functionality is disabled 

(either by fuse or by fw).

12

1b

RO

Indicates whether or not the entry's BRG_BA is configurable by host 

CPU. Hard coded to 1b, to ensure host CPU only access

11:8

X

RW

4 MS bits to be used for IOSF address, to be concatenated with the 

entry's BRG_BA_LSB[31:0] Locked by entry_valid bit.

7:4

0b

NA

RESERVED BITS

3:1

100b

RO

The target to which the SAP transaction will be redirected: 000 - Bridge 

memory space 001 - Bridge PCI configuration space 010 - IOSF sideband (General) 011 

- SPI via IOSF Sideband 100 - DDR via IOSF Primary Hard coded to '100' to let host 

configure TPM

0

X

RW

Entry valid bit. Entry hit condition is: ENTRY_VLD and SAP_BA (= 

SAPAddr[+SAPSize] ( SAP_BA + SAP_SIZE 1'b0: SATT TPM Entry is disabled. 1'b1: 

SATT TPM Entry is enabled. Note: when TPM disable fuse is '1', this bit is hard coded to 

'0'. Asserting this bit will lock the TPM SATT entries. (CTRL, BA and SIZE).

PCI Configuration Register

(Size: 32 bits)

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BR

G

_

B

A

31:0

X

RW

The bridge base address to be used for address translation using current 

SATT entry. Address calculation: FinalAddr = SAPAddr - SAP_BA + BRG_BA Locked by 

entry_valid bit in SATT1_CTRL register..

PCI Configuration Register

(Size: 32 bits)