Intel E3815 FH8065301567411 Data Sheet

Intel

Product codes

FH8065301567411

Intel

®

Atom™ Processor E3800 Product Family

Datasheet

3431

5C–5Fh

4

“Source Address Register for Channel 1 - High (SAR1_HI)—Offset 5Ch” on

00000000h

60–63h

4

“Destination Address Register for Channel 1 - Low (DAR1_LO)—Offset 60h” on

00000000h

64–67h

4

“Destination Address Register for Channel 1 - High (DAR1_HI)—Offset 64h” on

00000000h

68–6Bh

4

“Linked List Pointer Register for Channel 1 - Low (LLP1_LO)—Offset 68h” on

00000000h

6C–6Fh

4

“Linked List Pointer Register for Channel 1 - High (LLP1_HI)—Offset 6Ch” on

00000000h

70–73h

4

“Control Register for Channel 1 - Low (CTL1_LO)—Offset 70h” on page 3456

00304801h

74–77h

4

“Control Register for Channel 1 - High (CTL1_HI)—Offset 74h” on page 3457

00000002h

78–7Bh

4

“Source Status Register for Channel 1 - Low (SSTAT1_LO)—Offset 78h” on

00000000h

7C–7Fh

4

“Source Status Register for Channel 1 - High (SSTAT1_HI)—Offset 7Ch” on

00000000h

80–83h

4

“Dest Status Register for Channel 1 - Low (DSTAT1_LO)—Offset 80h” on

00000000h

84–87h

4

“Dest Status Register for Channel 1 - High (DSTAT1_HI)—Offset 84h” on

00000000h

88–8Bh

4

“Source Status Address Register for Channel 1 - Low (SSTATAR1_LO)—Offset

88h” on page 3460

00000000h

8C–8Fh

4

“Source Status Address Register for Channel 1 - High (SSTATAR1_HI)—Offset

8Ch” on page 3460

00000000h

90–93h

4

“Dest Status Address Register for Channel 1 - Low (DSTATAR1_LO)—Offset 90h”

00000000h

94–97h

4

“Dest Status Address Register for Channel 1 - High (DSTATAR1_HI)—Offset

94h” on page 3461

00000000h

98–9Bh

4

“Configuration Register for Channel 1 - Low (CFG1_LO)—Offset 98h” on

00000E20h

9C–9Fh

4

“Configuration Register for Channel 1 - High (CFG1_HI)—Offset 9Ch” on

00000004h

A0–A3h

4

“Source Gather Register for Channel 1 - Low (SGR1_LO)—Offset A0h” on

00000000h

A4–A7h

4

“Source Gather Register for Channel 1 - High (SGR1_HI)—Offset A4h” on

00000000h

A8–ABh

4

“Destination Scatter Register for Channel 1 - Low (DSR1_LO)—Offset A8h” on

00000000h

AC–AFh

4

“Dest Scatter Register for Channel 1 - High (DSR1_HI)—Offset ACh” on

00000000h

B0–B3h

4

“Source Address Register for Channel 2 - Low (SAR2_LO)—Offset B0h” on

00000000h

B4–B7h

4

“Source Address Register for Channel 2 - High (SAR2_HI)—Offset B4h” on

00000000h

B8–BBh

4

“Destination Address Register for Channel 2 - Low (DAR2_LO)—Offset B8h” on

00000000h

BC–BFh

4

“Destination Address Register for Channel 2 - High (DAR2_HI)—Offset BCh” on

00000000h

Table 251.

Summary of SIO DMA 1 Memory Mapped I/O Registers—BAR (Continued)

Offset

Size

(Bytes)

Register Name (Register Symbol)

Default

Value