Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

4082

Datasheet

Default: 00000008h

31:27

00h

RO

This 5-bit field indicates the power states in which the 

function may assert PME#. A value of 0b for any bit indicates that the function is not 

capable of asserting the PME# signal while in that power state. 
•

bit(11) X XXX1b - PME# can be asserted from D0. 

•

bit(12) X XX1Xb - PME# can be asserted from D1. Bridge does not support this 

state. 

•

bit(13) X X1XXb - PME# can be asserted from D2. Bridge does not support this 

state. 

•

bit(14) X 1XXXb - PME# can be asserted from D3hot. 

•

bit(15) 1 XXXXb - PME# can be asserted from D3cold. Bridge does not support this 

state. 

This field is taken from the strap strap_pme_support.

26:19

00h

RO

Reserved.

18:16

3h

RO

Indicates support for Revision 1.2 of the PCI Power Management 

Specification.

15:8

00h

RO

Points to the next capability structure. This points to 

NULL.

7:0

01h

RO

Indicates this is power 

management capability.

PCI Configuration Register

(Size: 32 bits)

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0

Re

se

rv

ed

0

PME

S

TA

TUS

Re

se

rv

ed

1

PM

EE

NA

BLE

Re

se

rv

ed

2

NO_SOF

T

_

RESET

Re

se

rv

ed

3

POW

E

RS

TA

TE

31:16

0000h

RO

Reserved.

15

0h

RW/1C

PME Status (PMESTATUS): 
•

0 = Software clears the bit by writing a 1 to it. 

•

1 = This bit is set when the AHB Device would normally assert the PME# signal 

independent of the state of the PME Enable bit (bit 8 in this register). 

14:9

00h

RO

Reserved.

8

0h

RW

A 1 enables the function to assert PME#. When 0, PME# 

message on SB is disabled.

7:4

0h

RO

Reserved.