Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
4273
Default: 00030001h
28.5.12
PME Control and Status Register (PMECTRLSTATUS)—Offset 84h
Access Method
Default: 00000008h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
PME
S
UPP
O
R
T
Re
se
rv
ed
0
VE
R
S
ION
NXT
C
AP
POW
E
R_C
A
P
Bit
Range
Default &
Access
Field Name (ID): Description
31:27
00h
RO
PME_Support (PMESUPPORT):
This 5-bit field indicates the power states in which the
function may assert PME#. A value of 0b for any bit indicates that the function is not
capable of asserting the PME# signal while in that power state.
•
•
bit(11) X XXX1b - PME# can be asserted from D0.
•
bit(12) X XX1Xb - PME# can be asserted from D1. Bridge does not support this
state.
•
bit(13) X X1XXb - PME# can be asserted from D2. Bridge does not support this
state.
•
bit(14) X 1XXXb - PME# can be asserted from D3hot.
•
bit(15) 1 XXXXb - PME# can be asserted from D3cold. Bridge does not support this
state.
This field is taken from the strap strap_pme_support.
26:19
00h
RO
Reserved0:
Reserved.
18:16
3h
RO
Version (VERSION):
Indicates support for Revision 1.2 of the PCI Power Management
Specification.
15:8
00h
RO
Next Capability (NXTCAP):
Points to the next capability structure. This points to
NULL.
7:0
01h
RO
Power Management Capability (POWER_CAP):
Indicates this is power
management capability.
Type:
PCI Configuration Register
(Size: 32 bits)
Offset:
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
Re
se
rv
ed
0
PM
ES
TA
TU
S
Re
se
rv
ed
1
PM
E
E
N
A
BL
E
Re
se
rv
ed
2
NO_SOF
T_RESET
Re
se
rv
ed
3
PO
WE
RST
A
TE
Bit
Range
Default &
Access
Field Name (ID): Description
31:16
0000h
RO
Reserved0:
Reserved.