Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
PCU – Power Management Controller (PMC)
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
4301
30.2
Features
30.2.1
Sx-G3-Sx, Handling Power Failures
Depending on when the power failure occurs and how the system is designed, different
transitions could occur due to a power failure.
transitions could occur due to a power failure.
The GEN_PMCON1.AG3E bit provides the ability to program whether or not the system
should boot once power returns after a power loss event. If the policy is to not boot,
the system remains in an S5 state (unless previously in S4). There are only two
possible events that will wake the system after a power failure.
should boot once power returns after a power loss event. If the policy is to not boot,
the system remains in an S5 state (unless previously in S4). There are only two
possible events that will wake the system after a power failure.
•
PMC_PWRBTN#: PMC_PWRBTN# is always enabled as a wake event. When
RSMRST# is low (G3 state), the PM1_STS_EN.PWRBTN_STS bit is reset. When the
SoC exits G3 after power returns (PMC_RSMRST# goes high), the PMC_PWRBTN#
signal is already high (because the suspend plane goes high before PMC_RSMRST#
goes high) and the PM1_STS_EN.PWRBTN_STS bit is 0b.
RSMRST# is low (G3 state), the PM1_STS_EN.PWRBTN_STS bit is reset. When the
SoC exits G3 after power returns (PMC_RSMRST# goes high), the PMC_PWRBTN#
signal is already high (because the suspend plane goes high before PMC_RSMRST#
goes high) and the PM1_STS_EN.PWRBTN_STS bit is 0b.
•
RTC Alarm: The PM1_STS_EN.RTC_EN bit is in the RTC well and is preserved after
a power loss. Like PM1_STS_EN.PWRBTN_STS the PM1_STS_EN.RTC_STS bit is
cleared when PMC_RSMRST# goes low.
a power loss. Like PM1_STS_EN.PWRBTN_STS the PM1_STS_EN.RTC_STS bit is
cleared when PMC_RSMRST# goes low.
The SoC monitors both PMC_CORE_PWROK and PMC_RSMRST# to detect for power
failures. If PMC_CORE_PWROK goes low, the GEN_PMCON1.PWR_FLR bit is set. If
PMC_RSMRST# goes low, GEN_PMCON1.SUS_PWR_FLR is set.
failures. If PMC_CORE_PWROK goes low, the GEN_PMCON1.PWR_FLR bit is set. If
PMC_RSMRST# goes low, GEN_PMCON1.SUS_PWR_FLR is set.
PMC_SUSCLK
O
V1P8A
Suspend Clock: This 32 kHz clock is an output of the
RTC generator circuit for use by other chips for refresh
clock.
This signal is muxed and may be used by other
functions.
RTC generator circuit for use by other chips for refresh
clock.
This signal is muxed and may be used by other
functions.
PMC_SUSPWRDNA
CK
CK
O
V1P8A
Suspend Power Down Acknowledge: Asserted by
the SoC on S0 to S4/5 transition when it does not
require its Suspend well to be powered. This pin
requires a pull-up to UNCORE_V1P8_G3.
This signal is muxed and may be used by other
functions.
the SoC on S0 to S4/5 transition when it does not
require its Suspend well to be powered. This pin
requires a pull-up to UNCORE_V1P8_G3.
This signal is muxed and may be used by other
functions.
PMC_WAKE_PCIE[3
:0]#
:0]#
I
V1P8A
PCI Express* Port [3:0] Wake Event: Sideband
wake signal on PCI Express asserted by a component
requesting wake up.
This signal is muxed and may be used by other
functions.
wake signal on PCI Express asserted by a component
requesting wake up.
This signal is muxed and may be used by other
functions.
PMC_PLT_CLK[5:0]
O
V1P8S
Platform Clocks: Configurable single ended clocks,
configurable to 25 MHz.
This signal is muxed and may be used by other
functions.
configurable to 25 MHz.
This signal is muxed and may be used by other
functions.
Table 287. PMC Signals (Sheet 3 of 3)
Signal Name
Direction
Plat. Power
Description