Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
PCU – Power Management Controller (PMC)
Intel
®
Atom™ Processor E3800 Product Family
4302
Datasheet
30.2.2
Event Input Signals and Their Usage
The SoC has various input signals that trigger specific events. This section describes
those signals and how they should be used.
those signals and how they should be used.
30.2.3
PCI Express* WAKE# Signal and PME Event Message
PCI Express ports can wake the platform from any sleep state (S3, S4, or S5) using the
PMC_WAKE_PCIE[3:0]# pins.
PMC_WAKE_PCIE[3:0]# pins.
Note:
PMC_WAKE_PCIE[3:0]# functionality is disabled by setting
PM1_STS_EN.PCIEXP_WAKE_DIS to 1b.
PM1_STS_EN.PCIEXP_WAKE_DIS to 1b.
PCI Express ports have the ability to cause PME using messages. When a PME message
is received, the SoC will set the GPE0a_STS.PCI_EXP_STS bit.
is received, the SoC will set the GPE0a_STS.PCI_EXP_STS bit.
30.2.3.1
PMC_PWRBTN# (Power Button)
The PMC_PWRBTN# signal operates as a “Fixed Power Button” as described in the
Advanced Configuration and Power Interface specification. The signal has a 16 ms
debounce on the input. The state transition descriptions are included in
Advanced Configuration and Power Interface specification. The signal has a 16 ms
debounce on the input. The state transition descriptions are included in
. Note
that the transitions start as soon as the PMC_PWRBTN# is pressed (but after the
debounce logic), and does not depend on when the power button is released.
debounce logic), and does not depend on when the power button is released.
Note:
During the time that the PMC_SLP_S4# signal is stretched for the minimum assertion
width (if enabled), the power button is not a wake event. Refer to note below for more
details.
width (if enabled), the power button is not a wake event. Refer to note below for more
details.
Table 288. Transitions Due to Power Failure
State at Power Failure
GEN_PMCON1.AG3E bit
Transition When Power Returns
S0, S3
1
0
0
S5
S0
S0
S4
1
0
0
S4
S0
S0
S5
1
0
0
S5
S0
S0