Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
4347
30.7.4
RST_CNT: Reset Control Register (RST_CNT)—Offset CF9h
Access Method
Default: 00h
Type:
I/O Register
(Size: 8 bits)
RST_CNT:
7
4
0
0
0
0
0
0
0
0
0
re
se
rv
ed
full_rs
t
rs
t_
cp
u
sys_rs
t
re
se
rv
ed
1
Bit
Range
Default &
Access
Description
7:4
0b
RO
reserved:
Reserved.
3
0b
RW
Full Reset (FULL_RST) (full_rst):
When this bit is set to 1 and bit 1 is set to 1
(indicating Hard Reset, not Soft Reset), and the RST_CPU bit (bit 2) is written from 0 to
1, the PMC will do a full reset, including driving PMU_SLP_S3_B and PMU_SLP_S4_B
active (low) for at least 3 (and no more than 5) seconds. When this bit is set, it also
causes the full power cycle (PMU_SLP_S3/4_B assertion) in response to
PMU_RESETBUTTON_B, COREPWROK, and Watchdog timer reset sources.
2
0b
RW
Reset CPU (RST_CPU) (rst_cpu):
This bit will cause either a hard or soft reset to the
CPU depending on the state of the SYS_RST bit (bit 1 in this same register). The
software will cause the reset by setting bit 2 from a 0 to a 1.
1
0b
RW
System Reset (SYS_RST) (sys_rst):
Ths bit determines the type of reset caused via
RST_CPU (bit 2 of this register). If SYS_RST is 0 when RST_CPU goes from 0 to 1, then
the PMC will force INIT# active for 16 PCI clocks. If SYS_RST is 1 when RST_CPU goes
from 0 to 1, then the PMC will force PCI reset active for about 1 ms, however the
PMU_SLP_S3_B and PMU_SLP_S4_B signals assertion is dependent on the value of the
FULL_RST (bit3 of this register).
0
0b
RO
reserved1:
Reserved.