Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
4349
Bit
Range
Default &
Access
Description
31
0b
RO
reserved4:
Reserved.
30
0b
RW
PCI Express Wake Disable (PCIEXP_WAKE_DIS) (pciexp_wake_dis):
This bit
disables the inputs to the PCIEXP_WAKE_STS bit in the PM1 Status register from waking
the system. Modification of this bit has no impact on the value of the
PCIEXP_WAKE_STS bit. reset_type=Resume Well Reset#
29
0b
RW
USB clockless Wake Enable (USB_CLKLESS_EN) (usb_clkless_en):
This bit
enables the inputs to the USB_CLKLESS_STS bit in the PM1 Status register to wake the
system. Modification of this bit has no impact on the value of the USB_CLKLESS_STS
bit. reset_type=Resume Well Reset#
28:27
0b
RO
reserved5:
Reserved.
26
0b
RW
RTC Alarm Enable (RTC_EN) (rtc_en):
This is the RTC alarm enable bit. It works in
conjunction with the SCI_EN bit: RTC_EN SCI_EN Effect when RTC_STS is set 0 x No
SMI# or SCI. If system was in S1-S5, no wake even occurs. 1 0 SMI#. If system was in
S1-S5, then a wake event occurs before the SMI#. 1 1 SCI. If system was in S1-S5,
then a wake event occurs before the SCI. Note: This bit needs to be backed by the RTC
well to allow an RTC event to wake after a power failure. In addition to being reset by
SRTCRST_B assertion, PMC also clears this bit due to certain events: - Power button
override - CPU thermal trip reset_type=SRTCRST_B
25
0b
RO
reserved6:
Reserved.
24
0b
RW
Power Button Enable (PWRBTN_EN) (pwrbtn_en):
This bit is the power button
enable. It works in conjunction with the SCI_EN bit: PWRBTN_EN SCI_EN Effect when
PWRBTN_STS is set 0 x No SMI# or SCI. 1 0 SMI#. 1 1 SCI. NOTE: PWRBTN_EN has no
effect on the PWRBTN_STS bit being set by the assertion of the power button. The
Power Button is always enabled as a Wake event. reset_type=Resume Well Reset#
23:22
0b
RO
reserved7:
Reserved.
21
0b
RW
Global Enable (GBL_EN) (gbl_en):
The global enable bit. When both the GBL_EN
and the GBL_STS are set, PMC generates an SCI. reset_type=PMU_PLTRST_B
20:17
0b
RO
reserved8:
Reserved.
16
0b
RW
Timer Overflow Interrupt Enable (TMROF_EN) (tmrof_en):
This is the timer
overflow interrupt enable bit. It works in conjunction with the SCI_EN bit: TMROF_EN
SCI_EN Effect when TMROF_STS is set 0 x No SMI# or SCI. . 1 0 SMI#. 1 1 SCI.
reset_type=PMU_PLTRST_B
15
0b
RW
Wake Status (WAK_STS) (wak_sts):
This bit is set when the system is in one of the
Sleep states (via the SLP_EN bit) and an enabled Wake event occurs. Upon setting this
bit, the PMC will transition the system to the ON state. This bit can only be set by
hardware and can only be cleared by writing a one to this bit position. This bit is not
affected by hard resets caused by a CF9 write, but is reset by RSMRST_B. If a power
failure occurs (such as removed batteries) without the SLP_EN bit set, the WAK_STS bit
will not be set when the power returns if the AFTER_G3 bit is 0. If the AFTER_G3 bit is
1, then the WAK_STS bit will be set after waking from a power failure. If necessary, the
BIOS can clear the WAK_STS bit in this case This is based on discussions with Microsoft.
That behavior is not in the ACPI spec. reset_type=RSMRST_B