Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
PCU – Serial Peripheral Interface (SPI)
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
4375
Single Input, Dual Output Fast Read
The SPI controller supports the functionality of a single input, dual output fast read:
Opcode 3Bh. This instruction has the same timing (including a dummy byte) and the
same frequencies as the Fast Read instruction, with the difference that the read data
from the Flash is presented on both the MISO and MOSI pins. During a Dual Read
instruction, the odd data bits are on the MISO pin and the even data bits are on the
MOSI pin.
Opcode 3Bh. This instruction has the same timing (including a dummy byte) and the
same frequencies as the Fast Read instruction, with the difference that the read data
from the Flash is presented on both the MISO and MOSI pins. During a Dual Read
instruction, the odd data bits are on the MISO pin and the even data bits are on the
MOSI pin.
Note:
When Dual Output Fast Read Support is enabled the Fast Read Support must be
enabled as well.
enabled as well.
Note:
Micronix* SPI Flash uses a different opcode for dual fast read, and requires that during
the address phase that the address bits are sent on both MOSI and MISO. The SoC
does not support this implementation of the protocol.
the address phase that the address bits are sent on both MOSI and MISO. The SoC
does not support this implementation of the protocol.
JEDEC ID
Since each serial Flash device may have unique capabilities and commands, the JEDEC
ID is the necessary mechanism for identifying the device so the uniqueness of the
device can be comprehended by the controller (master). The JEDEC ID uses the opcode
9Fh and a specified implementation and usage model. This JEDEC Standard
Manufacturer and Device ID read method is defined in Standard JESD21-C, PRN03-NV.
ID is the necessary mechanism for identifying the device so the uniqueness of the
device can be comprehended by the controller (master). The JEDEC ID uses the opcode
9Fh and a specified implementation and usage model. This JEDEC Standard
Manufacturer and Device ID read method is defined in Standard JESD21-C, PRN03-NV.
Figure 134.Dual Output Fast Read Timing
PCU_SPI_CS#
PCU_SPI_MOSI
PCU_SPI_MISO
PCU_SPI_CLK
23
22
21
2
1
0
0
1
2
3
4
5
6
7
8
9
10
29
30
31
Dual Output Fast Read
Opcode = 3Bh
24-bit address
PCU_SPI_CS#
PCU_SPI_MOSI
PCU_SPI_MISO
PCU_SPI_CLK
6
4
2
4
2
0
32
33
34
35
36
37
38
39
Dummy Byte
40
41
42
43
44
45
46
47
0
6
7
5
3
5
3
1
1
7
Read Data
Byte 0
Read Data
Byte 1
6
4
2
4
2
0
0
6
7
5
3
5
3
1
1
7
Read Data
Byte 2
Read Data
Byte 3
48
49
50
51
52
53
54
55
MOSI switches from
input to output