Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
PCU – Serial Peripheral Interface (SPI)
Intel
®
Atom™ Processor E3800 Product Family
4376
Datasheet
Error Correction and Detection
If the first 8 bits specify an opcode which is not supported the slave will not respond
and wait for the next high to low transition on PCU_SPI_CS[1:0]#. The SPI controller
should automatically discard 8 bit words that were not completely received upon de-
assertion of the signal.
and wait for the next high to low transition on PCU_SPI_CS[1:0]#. The SPI controller
should automatically discard 8 bit words that were not completely received upon de-
assertion of the signal.
Any other error correction or detection mechanisms must be implemented in firmware
and/or software.
and/or software.
31.2.6
Multiple Page Write Usage Model
The BIOS and Trusted Execution Engine firmware usage models require that the serial
Flash device support multiple writes to a page (minimum of 512 writes) without
requiring a preceding erase command. The BIOS commonly uses capabilities such as
counters that are used for error logging and system boot progress logging. These
counters are typically implemented by using byte-writes to ‘increment’ the bits within a
page that have been designated as the counter. The Trusted Execution Engine firmware
usage model requires the capability for multiple data updates within any given page.
These data updates occur using byte-writes without executing a preceding erase to the
given page. Both the BIOS and Trusted Execution Engine firmware multiple page write
usage models apply to sequential and non-sequential data writes.
Flash device support multiple writes to a page (minimum of 512 writes) without
requiring a preceding erase command. The BIOS commonly uses capabilities such as
counters that are used for error logging and system boot progress logging. These
counters are typically implemented by using byte-writes to ‘increment’ the bits within a
page that have been designated as the counter. The Trusted Execution Engine firmware
usage model requires the capability for multiple data updates within any given page.
These data updates occur using byte-writes without executing a preceding erase to the
given page. Both the BIOS and Trusted Execution Engine firmware multiple page write
usage models apply to sequential and non-sequential data writes.
This usage model requirement is based on any given bit only being written once from a
‘1’ to a ‘0’without requiring the preceding erase. An erase would be required to change
bits back to the 1 state.
‘1’ to a ‘0’without requiring the preceding erase. An erase would be required to change
bits back to the 1 state.
31.2.7
Soft Flash Protection
There are two types of Flash protection that are not defined in the Flash descriptor
supported by the SPI controller:
supported by the SPI controller:
1. Flash Range Read and Write Protection
2. Global Write Protection
31.2.7.1
Flash Range Read and Write Protection
The SPI controller provides a method for blocking reads and writes to specific ranges in
the Flash when the Protected Ranges are enabled. This is achieved by checking the
read or write cycle type and the address of the requested command against the base
and limit fields of a Read or Write Protected range. Protected range registers are only
applied to Programmed Register accesses and have no effect on Direct Reads.
the Flash when the Protected Ranges are enabled. This is achieved by checking the
read or write cycle type and the address of the requested command against the base
and limit fields of a Read or Write Protected range. Protected range registers are only
applied to Programmed Register accesses and have no effect on Direct Reads.
Note:
Once BIOS has locked down the Protected BIOS Range registers, this mechanism
remains in place until the next system reset.
remains in place until the next system reset.