Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
PCU – Serial Peripheral Interface (SPI)
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
4379
BIOS must properly set up the SoC to account for this. The Host VSCC registers and
VSCC Table have to be correctly configured for BIOS and Security Engine have read/
write access to SPI.
VSCC Table have to be correctly configured for BIOS and Security Engine have read/
write access to SPI.
31.3.1.2
Software Sequencing
All commands other than the standard (memory) reads must be programmed by the
software in the Software Sequencing Control, Flash Address, Flash Data, and Opcode
configuration registers. Software must issue either Read ID or Read JEDEC ID, or a
combination of the two to determine what Flash component is attached. Based on the
Read ID, software can determine the appropriate Opcode instructions sets to set in the
program registers and at what SPI frequency to run the command.
software in the Software Sequencing Control, Flash Address, Flash Data, and Opcode
configuration registers. Software must issue either Read ID or Read JEDEC ID, or a
combination of the two to determine what Flash component is attached. Based on the
Read ID, software can determine the appropriate Opcode instructions sets to set in the
program registers and at what SPI frequency to run the command.
Software must program the Flash Linear Address for all commands, even for those
commands that don't require address such as the Read ID or Read Status. This is
because the SPI controller uses the address to determine which chip select to use.
commands that don't require address such as the Read ID or Read Status. This is
because the SPI controller uses the address to determine which chip select to use.
The opcode type and data byte count fields determine how many clocks to run before
deasserting the chip enable. The Flash data is always shifted in for the number of bytes
specified and the Flash Data out is always shifted out for the number of data bytes
specified. Note that the hardware restricts the burst lengths that are allowed.
deasserting the chip enable. The Flash data is always shifted in for the number of bytes
specified and the Flash Data out is always shifted out for the number of data bytes
specified. Note that the hardware restricts the burst lengths that are allowed.
A status bit indicates when the cycle has completed on the SPI port allowing the host to
know when read results can be checked and/or when to initiate a new command.
know when read results can be checked and/or when to initiate a new command.
The controller also provides the “Atomic Cycle Sequence” for performing erases and
writes to the SPI Flash. When this bit is 1 (and the Go bit is written to 1), a sequence of
cycles is performed on the SPI interface without allowing other SPI device to arbitrate
and interleave cycles to the Flash device. In this case, the specified cycle is preceded
by the Prefix Command (8-bit programmable Opcode) and followed by repeated reads
to the Status Register (Opcode 05h) until bit 0 indicates the cycle has completed. The
hardware does not attempt to check that the programmed cycle is a write or erase.
writes to the SPI Flash. When this bit is 1 (and the Go bit is written to 1), a sequence of
cycles is performed on the SPI interface without allowing other SPI device to arbitrate
and interleave cycles to the Flash device. In this case, the specified cycle is preceded
by the Prefix Command (8-bit programmable Opcode) and followed by repeated reads
to the Status Register (Opcode 05h) until bit 0 indicates the cycle has completed. The
hardware does not attempt to check that the programmed cycle is a write or erase.
If a Programmed Access is initiated (Cycle Go written to 1) while the SPI controller is
already busy with a Direct Memory Read, then the SPI Host hardware will hold the new
Programmed Access pending until the preceding SPI access completes.
already busy with a Direct Memory Read, then the SPI Host hardware will hold the new
Programmed Access pending until the preceding SPI access completes.
Once the SPI controller has committed to running a programmed access, subsequent
writes to the programmed cycle registers that occur before it has completed will not
modify the original transaction and will result in the assertion of the FCERR bit.
Software should never purposely behave in this way and rely on this behavior. However,
the FCERR bit provides basic error-reporting in this situation. Writes to the following
registers cause the FCERR bit assertion in this situation:
writes to the programmed cycle registers that occur before it has completed will not
modify the original transaction and will result in the assertion of the FCERR bit.
Software should never purposely behave in this way and rely on this behavior. However,
the FCERR bit provides basic error-reporting in this situation. Writes to the following
registers cause the FCERR bit assertion in this situation:
•
Software Sequencing Control
•
Software Sequencing Address
•
SPI Data