Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
 
PCU – Intel
®
 Legacy Block (iLB) Overview
Intel
®
 Atom™ Processor E3800 Product Family
Datasheet
4479
34.2
Features
34.2.1
Key Features
The key features of various blocks are as follows:
Subtractive agent for the PCU
LPC Interface
— Supports Low Pin Count (LPC) 1.1 Specification
— No support for DMA or bus mastering
— Supports Trusted Platform Module (TPM) 1.2
— Subtractive agent for the Intel Legacy Block
General Purpose Input Output
— Control interface for SoC GPIOs
— I/O mapped registers
8259 Programmable Interrupt Controller
— Legacy interrupt support
— 15 total interrupts through two cascaded controllers
— I/O and Memory mapped registers
I/O Advanced Programmable Interrupt Controller
— Legacy-free interrupt support
— 87 total interrupts
— Memory mapped registers
8254
— Legacy  timer  support
— Three timers with fixed uses: System Timer, Refresh Request Signal and 
Speaker Tone
— I/O mapped registers
HPET - High Performance Event Timers
— Legacy-free timer support
Table 317. iLB Signals 
Signal Name
Direction
Plat. Power
Description
ILB_NMI
I
V1P8S
Non-Maskable Interrupt: This is an NMI event indication into 
the SoC. 
This signal is muxed and may be used by other functions.