Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

4480

Datasheet

— Three timers and one counter

— Memory mapped registers

•

Real-Time Clock (RTC)

— 242 byte RAM backed by battery (aka CMOS RAM)

— Can generate wake/interrupt when time matches programmed value

— I/O and indexed registers

NMI support is enabled by setting the NMI Enable (NMI_EN) bit, at IO Port 70h, Bit 7, 
to 0b. 

Non-Maskable Interrupts (NMIs) can be generated by several sources, as described in 

§ 

SERR# goes active 
NOTE: A SERR# is only generated 

internally in the SoC)

NSC.SNE

NSC.SNS

All NMI sources may, 
alternatively, generate a 
SMI by setting 
GNMI.NMI2SMIEN=1b 

The SoC uses 
GNMI.NMI2SMIST for 
observing SMI status

IOCHK# goes active 
NOTE: A IOCHK# is only generated 

as a SERIRQ# frame 

NSC.INE

NSC.INS

ILB_NMI goes active
NOTE: Active can be defined as 

being on the positive or 
negative edge of the signal 
using the GNMI.GNMIED 
register bit.

GNMI.GNMIED GNMI.GNMIS

Software sets the GNMI.NMIN 
register bit

GNMI.NMIN

GNMI.NMINS