Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
PCU – iLB – GPIO
Intel
®
Atom™ Processor E3800 Product Family
4572
Datasheet
39
PCU – iLB – GPIO
102 GPIOs are available for use during the S0 ACPI state, and 44 are available for use
from S5 to S0 (SUS). Most of these GPIOs can be used as legacy GPIOs through IO
registers.
from S5 to S0 (SUS). Most of these GPIOs can be used as legacy GPIOs through IO
registers.
39.1
Signal Descriptions
Please see
for additional details.
The signal description table has the following headings:
•
Signal Name: The name of the signal/pin
•
Direction: The buffer direction can be either input, output, or I/O (bidirectional)
•
Platform Power: The reference power plane
•
Description: A brief explanation of the signal’s function
39.2
Features
GPIOs can generate general purpose events (GPEs) on rising and/or falling edges.
I
O
I
O
I
O
I
O
I
O
I
O
O
Platform Control Unit
UAR
T
LPC
GPIO
RTC
HPET
8
259
APIC
8
254
iLB
SP
I
I
PMC
I
O
SMB
Table 336. GPIO Signals
Signal Name
Direction
Plat. Power
Description
GPIO_S0_SC[101:0]
I/O
Varies
These GPIO pins are powered and active in S0 only.
Many of these are multiplexed with other functions and
may have different default pin names.
Many of these are multiplexed with other functions and
may have different default pin names.
GPIO_S5[43:0]
I/O
Varies
These GPIO pins are powered and active in S5-S0
(SUS). Many of these are multiplexed with other
functions and may have different default pin names.
Some are used as straps.
(SUS). Many of these are multiplexed with other
functions and may have different default pin names.
Some are used as straps.