Intel N2820 FH8065301616603 Data Sheet
Product codes
FH8065301616603
PCU – Serial Peripheral Interface (SPI)
1054
Datasheet
Single Input, Dual Output Fast Read
The SPI controller supports the functionality of a single input, dual output fast read:
Opcode 3Bh. This instruction has the same timing (including a dummy byte) and the
same frequencies as the Fast Read instruction, with the difference that the read data
from the Flash is presented on both the MISO and MOSI pins. During a Dual Read
instruction, the odd data bits are on the MISO pin and the even data bits are on the
MOSI pin.
Opcode 3Bh. This instruction has the same timing (including a dummy byte) and the
same frequencies as the Fast Read instruction, with the difference that the read data
from the Flash is presented on both the MISO and MOSI pins. During a Dual Read
instruction, the odd data bits are on the MISO pin and the even data bits are on the
MOSI pin.
Note:
When Dual Output Fast Read Support is enabled the Fast Read Support must be
enabled as well.
enabled as well.
Note:
Micronix* SPI Flash uses a different opcode for dual fast read, and requires that during
the address phase that the address bits are sent on both MOSI and MISO. The
processor does not support this implementation of the protocol.
the address phase that the address bits are sent on both MOSI and MISO. The
processor does not support this implementation of the protocol.
Read Status
05h
Outputs contents of SPI Flash’s status register
Write Enable
06h
Fast Read
0Bh
Enable Write to Status
Register
50h
Enables a bit in the status register to allow an update to the
status register
Erase
Programmable
Uses the value from LVSSC.LEO register or UVSSC.UEO
register depending on the FLA and whether it is below or
above the FPBA respectively
Table 157. Hardware Sequencing Commands and Opcode Requirements (Sheet 2 of 2)
Commands
Opcode
Notes