Intel N2820 FH8065301616603 Data Sheet
Product codes
FH8065301616603
PCU – Serial Peripheral Interface (SPI)
1056
Datasheet
page that have been designated as the counter. The Trusted Execution Engine firmware
usage model requires the capability for multiple data updates within any given page.
These data updates occur using byte-writes without executing a preceding erase to the
given page. Both the BIOS and Trusted Execution Engine firmware multiple page write
usage models apply to sequential and non-sequential data writes.
usage model requires the capability for multiple data updates within any given page.
These data updates occur using byte-writes without executing a preceding erase to the
given page. Both the BIOS and Trusted Execution Engine firmware multiple page write
usage models apply to sequential and non-sequential data writes.
This usage model requirement is based on any given bit only being written once from a
‘1’ to a ‘0’without requiring the preceding erase. An erase would be required to change
bits back to the 1 state.
‘1’ to a ‘0’without requiring the preceding erase. An erase would be required to change
bits back to the 1 state.
21.2.7
Soft Flash Protection
There are two types of Flash protection that are not defined in the Flash descriptor
supported by the SPI controller:
supported by the SPI controller:
1. Flash Range Read and Write Protection
2. Global Write Protection
21.2.7.1
Flash Range Read and Write Protection
The SPI controller provides a method for blocking reads and writes to specific ranges in
the Flash when the Protected Ranges are enabled. This is achieved by checking the
read or write cycle type and the address of the requested command against the base
and limit fields of a Read or Write Protected range. Protected range registers are only
applied to Programmed Register accesses and have no effect on Direct Reads.
the Flash when the Protected Ranges are enabled. This is achieved by checking the
read or write cycle type and the address of the requested command against the base
and limit fields of a Read or Write Protected range. Protected range registers are only
applied to Programmed Register accesses and have no effect on Direct Reads.
Note:
Once BIOS has locked down the Protected BIOS Range registers, this mechanism
remains in place until the next system reset.
remains in place until the next system reset.
21.2.7.2
Global Write Protection
The SPI controller has a Write Protection Disable (BCR.WPD) configuration bit. When
BCR.WPD=0b, BIOS is not able to perform any write or erase commands to the Flash.
When BCR.WPD=1b, protection against BIOS erase and rewrite is disabled. When the
lock enable (BCR.LE) bit is set, the BIOS can disable this protection only during System
Management Mode (SMM) execution.
BCR.WPD=0b, BIOS is not able to perform any write or erase commands to the Flash.
When BCR.WPD=1b, protection against BIOS erase and rewrite is disabled. When the
lock enable (BCR.LE) bit is set, the BIOS can disable this protection only during System
Management Mode (SMM) execution.
If BCR.LE=1b, the SPI controller confirms that only SMM code succeeds to set
BCR.WPD=1b. In addition, if BCS.SMIWPEN=1b, the SPI controller should initiate an
SMI when non SMM code tries to set BCR.WPD=1b.
BCR.WPD=1b. In addition, if BCS.SMIWPEN=1b, the SPI controller should initiate an
SMI when non SMM code tries to set BCR.WPD=1b.
21.2.8
SPI Flash Device Recommended Pinout
This table contains the recommended serial Flash device pin-out for an 8-pin device.
Use of the recommended pin-out on an 8-pin device reduces complexities involved with
designing the serial Flash device onto a motherboard and allows for support of a
common footprint usage model (refer to
Use of the recommended pin-out on an 8-pin device reduces complexities involved with
designing the serial Flash device onto a motherboard and allows for support of a
common footprint usage model (refer to