Intel N2820 FH8065301616603 Data Sheet

Datasheet

1137

7

0b

RW

PECEN: PEC_EN: When set to '1', this bit causes the host controller to perform the 

SMBus transaction with the Packet Error Checking phase appended. For writes, the 

value of the PEC byte is transferred from the PEC Register. For reads, the PEC byte is 

loaded in to the PEC Register. When this bit is cleared to '0', the SMBus host controller 

does not perform the transaction with the PEC phase appended. This bit must be written 

prior to the write in which the START bit is set.

6

0b

WO

START (SATRT): START: This write-only bit is used to initiate the command described 

in the SMB_CMD field. All registers should be setup prior to writing a '1' to this bit 

position. This bit always reads zero. The HOST_BUSY bit in the Host Status register 

(offset 00h) can be used to identify when the SMBus controller has finished the 

command.

4:2

000b

RW

SMBCMD: SMB_CMD - As shown by the bit encoding below, indicates which command 

the SMBus host is to perform. If enabled, the SMBus host will generate an interrupt or 

SMI when the command has completed If the value is for a non-supported or reserved 

command, the SMBus host will set the device error (DEV_ERR) status bit and generate 

an interrupt when the START bit is set. The SMBus controller will perform no command, 

and will not operate until DEV_ERR is cleared.3'b000 - Quick
The slave address and read/write value (bit 0) are stored in the tx slave address register
3'b001 - Byte
This command uses the transmit slave address and command registers. Bit 0 of the 

slave address register determines if this is a read or write command. If it is a read, after 

the command completes the DATA0 register will contain the read data.
3'b010 - Byte Data
This command uses the transmit slave address, command, and DATA0 registers. Bit 0 of 

the slave address register determines if this is a read or write command. If it is a read, 

the DATA0 register will contain the read data
3'b011 - Word Data
This command uses the transmit slave address, command, DATA0 and DATA1 registers. 

Bit 0 of the slave address register determines if this is a read or write command. If it is 

a read, after the command completes the DATA0 and DATA1 registers will contain the 

read data.
3'b100 - Process Call
This command uses the transmit slave address, command, DATA0 and DATA1 registers. 

Bit 0 of the slave address register determines if this is a read or write command. After 

the command completes, the DATA0 and DATA1 registers will contain the read data.
3'b101 - Block
This command uses the transmit slave address, command, and DATA0 registers, and the 

Block Data Byte register. For block write, the count is stored in the DATA0 register and 

indicates how many bytes of data will be transferred. For block reads, the count is 

received and stored in the DATA0 register. Bit 0 of the slave address register selects if 

this is a read or write command. For writes, data is retrieved from the first n (where n is 

equal to the specified count) addresses of the SRAM array. For reads, the data is stored 

in the Block Data Byte register.
3'b111 - Block Process
This command uses the transmit slave address, command, DATA0 and the Block Data 

Byte register. For block write, the count is stored in the DATA0 register and indicates 

how many bytes of data will be transferred. For block read, the count is received and 

stored in the DATA0 register. Bit 0 of the slave address register always indicate a write 

command. For writes, data is retrieved from the first m (where m is equal to the 

specified count) addresses of the SRAM array. For reads, the data is stored in the Block 

Data Byte register. Note: E32B bit in the Auxiliary Control Register must be set 

1

0b

RW

KILL: KILL - When set, kills the current host transaction taking place, sets the FAILED 

status bit, and asserts the interrupt (or SMI) selected by the SMB_Cfg_HCFG.SMI_EN 

field. This bit, once set, must be cleared to allow the SMB Host Controller to function 

normally

0

0b

RW

INTREN: Enable the generation of an interrupt or SMI upon the completion of the 

command. Enables also other interrupt sendings , like ALERT and HOST_NOTIFY