Intel N2820 FH8065301616603 Data Sheet

Datasheet

1207

In order to meet LPC interface AC timing requirements, a LPC clock loop back is 
required. The operation of this loop back can be configured in two ways:

1. On the processor: In this configuration, ILB_LPC_CLK[0] is looped back on itself on 

the processor pad. 

a. Benefit: 

ILB_LPC_CLK[0] and ILB_LPC_CLK[1] are both available for system clocking

b. Drawback:

Clock delay compensation is less effective at compensating for mainboard delay

c. Soft Strap & Register Requirements:

Soft Strap LPCCLK_SLC = 0b

Configuration is reflected by register bit LPCC.LPCCLK_SLC=0b

Soft Strap LPCCLK1_ENB = 0b (ILB_LPC_CLK[1] disabled)  or 1b (ILB_LPC_CLK[1] 
enabled) 

2. Configuration is reflected by register bit LPCC.LPCCLK1EN=0b (ILB_LPC_CLK[1] 

disabled)  or 1b (ILB_LPC_CLK[1] enabled)  

3. On the main board: In this configuration, ILB_LPC_CLK[0] is looped back to 

ILB_LPC_CLK[1] on the main board. 

a. Benefit: 

Clock delay compensating in more effective at compensating for main board delay

b. Drawback:

Only ILB_LPC_CLK[0] is available for system clocking. ILB_LPC_CLK[1] must be 
disabled.

c. Soft Strap & Register Requirements:

Soft Strap LPCCLK_SLC = 1b

Configuration is reflected by register bit LPCC.LPCCLK_SLC=1b

Soft Strap LPCCLK1_ENB = 0b (ILB_LPC_CLK[1] disabled) 

Configuration is reflected by register bit LPCC.LPCCLK1EN=0b